ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 2

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

switching losses in high frequency, high input voltage, and
/or high current applications. The switching losses can be
reduced by employing snubbers, or quasi- or fully resonant,
soft-switching circuits [1].
In the ISL6551, rather than driving both of the diagonal full
bridge switches together, the two upper switches (QA & QC)
NOTE: Pin numbers in the diagram refer to the SOIC package.
R_RESDLY
Circuits Referenced to VSS
VP
A
B
D
C
FIGURE 2. CONVENTIONAL FULL BRIDGE PWM
PKILIM
ISENSE
BGREF
BGREF
R_LEB
R_RA
EANI
EAO
EAI
CT
RD
14
13
12
7
9
4
5
2
3
6
8
WAVEFORMS
ON
REFERENCE
BANDGAP
GENERATOR
RESODLY
RESODLY
ERROR
CLOCK
DC OK
ADJUST
ADJUST
AMP
RAMP
RAMP
ON
2
FIGURE 3. ISL6551 INTERNAL STRUCTURE
CURRENT
SHARE
Application Note 1002
UVLO
LEB
LOGIC
PWM
SHUTDOWN
SHUTDOWN
are driven at a fixed 50% duty cycle and the two lower
switches (QB & QD) are PWM-controlled on the trailing edge
while the leading edge employs resonant delay. Figure 4
shows the drive signals of four bridge FETs and three
options for synchronous rectification. The basic control
principle of the ISL6551 is different from that of the
UC3875’s phase-shift control which varies the phase
between two 50% duty cycle control signals [1], requiring
additional circuitry to derive the synchronous control signals
and therefore adding cost.
The ISL6551 is a ZVS full bridge controller that Intersil has
designed for medium to high power AC/DC and DC/DC
applications with ultra high efficiency requirements. The
ISL6551 includes many integrated features for a more
complete and sophisticated telecom or off-line power supply
solution. The internal architecture of the IC is shown in
Figure 4. Detailed ZVS operation of the ISL6551 will be
presented by describing switching actions of the power train
at each time interval in the following sections. Refer to the
device datasheet for the operation of the integrated features.
SHUTDOWN
SHUTDOWN
LATCH
LATCH
External Single Point Connection Required
START
START
SOFT
SOFT
UPPER1
DRIVER
LOWER1
DRIVER
LOWER2
DRIVER
UPPER2
DRIVER
Circuits Referenced to PGND
27
24
26
23
22
21
VDDP2
VDDP1
UPPER1
UPPER2
LOWER1
LOWER2