ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 8

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

T7 --> T8=To, Lower Right-Leg (QD) Resonant
Period [Figure 13]
The previous dead time period is followed by the lower right-
leg resonant period. It begins with QC turned off and QA
turned on. At the beginning of this transition, the input
voltage is applied first across the commutating inductance
(leakage and any external inductances), i.e, the real primary
stays zero until the current through these inductors changes
in direction in the next time interval. This can be seen in the
voltage waveforms across the primary winding and the
secondary winding, discussed in the EXPERIMENTAL
RESULTS section on page 24-25. The direction of the
current through the primary winding remains the same as
that in the previous time interval. The current flows into the
transformer primary capacitance (Cp) and the output
capacitance (Coss) CC of QC, which will be charged up from
zero voltage (~Rds(on) Drop) to V
output capacitance CD of QD is discharged to from V
Rds(on) Drop to zero voltage (~diode drop). This transition is
accomplished with the energy stored in the primary
inductance (including leakage inductance, magnetizing
inductance, and any external inductance). It takes a longer
time to complete this transition than the one reaching the
freewheeling period since the energy stored in the resonant
inductance decreases due to the conduction losses of the
power switches and the primary current is decaying in the
freewheeling period. Once QD is clamped to zero voltage by
its own body diode, QD is turned on at zero voltage (ZVS
transition). At this point a full operating cycle is completed.
+
QA
Vin
QB
-
SYNC DRIVE
INV_LOW DRIVE
INV_SYNC DRIVE
SYNCHRONOUS FETS
-
DA
CA
DB
CB
QB = OFF, QC = ON, QA = QD = OFF
FIGURE 12. DEAD TIME PERIOD
Lk
-
Vp
Vs
Q1
Cp
Q2
8
T
+
IN
OFF
ON
ON
QC
QD
Q1
. Simultaneously, the
+
D1
D2
Lo1
Lo2
DC
CC
DD
CD
Application Note 1002
ON
ON
ON
Q2
IN
-
Vo
Co
Intersil Supervisor and Monitor: ISL6550
The ISL6550 is a precision flexible, VID-code-controlled
reference and voltage monitor for high-end microprocessor
and memory power supplies. It monitors various input
signals, and supervises the systems with its outputs. The
ISL6550 saves board space, design time, and system cost.
The internal structure of the ISL550 is shown in Figure 14.
The reference design is implemented with the MLFP-
packaged ISL6550, C version. Refer to the device datasheet
for operating details.
In the reference design, the ISL6550 monitors the output
voltage and supervises the ISL6551 full bridge controller.
• The spare operational amplifier of the ISL6550 is used as
• The under-voltage delay (UVDLY) prevents false triggering
• The output reference BDAC, which is fed to the non-
+
QA
Vin
QB
-
a differential amplifier and its output (VOPOUT) is sent to
the inverting input (EAI) of the error amplifier of the
ISL6551. Note that the VOPOUT is limited to 5V.
of the START output during startup, and the ISL6550
START output is fed to the ON/OFF input of the ISL6551.
In output over-voltage (+8.33%) and under-voltage (-
8.33%) conditions, the START is triggered and latches
shutdown the ISL6551 controller. When the VCC of
ISL6550 is below the turn-on/off threshold, the START is
held low and disables the ISL6651 controller.
inverting input (EANI) of the error amplifier of the ISL6551,
is programmed by the 5-bit VIDs and the resistor network
that connects to DACHI and DACLO. Note that a 50k total
resistance of the network is recommended and the overall
SYNC DRIVE
INV_LOW DRIVE
INV_SYNC DRIVE
SYNCHRONOUS FETS
FIGURE 13. LOWER RIGHT-LEG RESONANT PERIOD
-
DA
CA
DB
CB
QC = OFF, QA = ON, QB = QD = OFF
Lk
-
Vp
Vs
Q1
Cp
Q2
T
+
QC
QD
ON
ON
ON
Q1
+
D1
D2
Lo1
Lo2
DC
CC
DD
CD
OFF
OFF
OFF
Q2
Vo
Co