ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 12

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

given dI/dt, that adds on the top of the existing voltage
undershoot/overshoot due to the ESR and capacitance.
Thus, the overall output voltage undershoot/overshoot due to
load transients can be summarized in EQ. 18, in which the
last term can be normally dropped out if the very edge of the
transient is the dominant peak, as shown in Figure 16.
The last term in EQ. 18 is a direct consequence of the
amount of output capacitance. After the initial spike, all the
excessive charge is dumped into the output capacitors on
step-down transients causing a temporary hump at the
output, and the output capacitors deliver extra charge to
meet the load demand on step-up transients causing a
temporary sag before the output inductors catch the load.
The approximate response time intervals for removal and
application of a transient load are defined by dTn and dTp,
respectively.
In low-profile, high current density, and high frequency
applications, the required output capacitance defined in
EQ. 13 might not be enough to deliver or absorb energy due
∆V
dVtr
∆V
∆V
FIGURE 16. TYPICAL TRANSIENT RESPONSE WAVEFORM
Vo
f(Istep)
ESL
where
HUMP
SAG
where
where
∆V
≈
Istep
f Istep
(
=
ESL
∆
f Istep
∆
f Istep
f Istep
(
(
=
(
V
V
ESL
=
CAP
CAP
Istep dTp
-------------------------------
Istep dTn
-------------------------------
)
2 Co
•
+
) Istep ESR
2 Co
)
)
•
=
=
dI
---- -
dt
≈
≈
∆V
•
=
•
∆
------------------------------ -
2π f
∆
•
Istep
V
ESL
V
dTp
dTn
HUMP
SAG
Istep
•
c
•
+
----------------------------------------------------------------------- -
•
=
∆
=
1
Co
V
Lo
Lo
+
CAP
12
(
------------------------ -
Vs 2Vo
2π f
Istep
--------------
2Vo
Istep
2π f
for
for
for
for
–
•
•
c
∆V
•
c
Co ESR
•
CAP
Co
step-down transients
fc
fc
step-up transients
•
≥
≤
--------------------------------------- -
2π ESR
--------------------------------------- -
2π ESR
•
•
)
2
Application Note 1002
1
1
(EQ. 19)
(EQ. 17)
(EQ. 18)
(EQ. 20)
•
•
Co
Co
to load transients. This could cause a significantly large
undershoot/overshoot at the output. In the reference design,
the loop bandwidth (f
[1/(2π*ESR*Co)] of the output capacitors, which have low
ESL transient component due to low dI/dt(1A/us), therefore,
the required output capacitance can be roughly
approximated with EQ. 21 [7].
Several lower-profile TAIYO YUDEN 100u, 6.3V capacitors
(JMK212F107MM) have been used in the evaluation board
to meet the electrical requirements of the above discussion
and the height constraint of the converter.
Besides ESL, ESR, and capacitance of the output
capacitors, other system parasitics such as board resistance
and inductance should be included in the load transient
analysis [6], which will not be discussed in this paper.
Electrical design parameters of the output inductors are
summarized in EQs. 11, 22, & 23, which specify the ripple
current, the peak current, and the RMS current of each
inductor.
Calculations for Synchronous FETs (Q1 & Q2)
Some fundamental formulas that are used to calculate RMS
values of triangular and trapezoid waveforms and to derive
most equations in this paper are defined below.
CASE 1
In the power transfer period, one synchronous FET is turned
off, and the other one is turned on conducting all the load
CASE 3
CASE 2
Irms2
Iindpeak
Iindrms
Irms1
Irms3
Co
≈
=
=
=
---------------------------------- -
2π f
=
=
0


Ic
•
Ic
Io
---- -
Istep
Ic
2
I ∆
Io
---------------- -
2
c
2
2
+
+
•
•
+
+
2
----------
Ia
∆
------- -
dVtr
(
12
dI
dI
∆
------- -
d d
12
Ia
12
I
2
I
2
–


c
•
2
1 d
) is lower than the zero
d
)
–
Ib
+
d
∆
------- - d
12
Ib
I
2
•
Ia
I ∆
fc
d
≤
--------------------------------------- -
2π ESR
Ib
•
I ∆
1
d
•
Co
(EQ. 21)
(EQ. 22)
(EQ. 23)
Ic
–
Ic
0
Id