ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 27

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

As shown in Figures 35 and 36, the synchronous FETs are
zero-voltage switching at turn on, and have negligible
switching losses at turn off during the light load. Nevertheless,
the two bumps, as shown in Figure 35, are caused by the
body diode conduction and/or its reverse recovery at turn on
or off, which do induce losses.
Shutdown Timing (Shorted Circuit, UV, OV)
OUTPUT SHORTED CIRCUIT
When the output is shorted, the START (channel 2) is
latched after the UVDLY (channel 3) capacitor (C26) is
charged above the threshold 5V, as shown in Figure 37.
Note that additional delay is induced by the probe at the
ISL6550 UVDLY pin. If the short is removed and the output
voltage returns to the normal level before the under-voltage
delay, around 70ms, is time out, then the START would not
be latched.
OUTPUT UNDER-VOLTAGE DELAY
As shown in Figure 38, the output voltage (Channel 3) has a
huge dip, but it returns to normal level before the under-
voltage delay is time out, hence, the START (channel 2) is
not pulled low. Figure 39 shows that the UVDLY starts to rise
when the output voltage is below the under-voltage
threshold, and the START is latched when the UVDLY
reaches 5V threshold.
FIGURE 37. OUTPUT SHORTED CIRCUIT. CHANNEL 1:
OUTPUT VOLTAGE; CHANNEL 2: START
SIGNAL; CHANNEL 3: UVDLY AT ISL6550;
CHANNEL 4: OUTPUT CURRENT
27
Application Note 1002
OUTPUT OVER-VOLTAGE
When the EAI pin is pulled to ground, the error voltage jumps
up and causes an over voltage at the output (channel 1), and
the START (Channel 3) is latched, as shown in Figure 40.
The LATSD (Channel 2) is not triggered since the output
voltage does not exceed the master over-voltage setpoint.
With a quick touch to the output (at zero load) with a 5V
voltage source, both local and master over-voltage setpoints
are violated. Figure 41 shows that the START is triggered at
a lower voltage level than the LATSD. The START is
nominally latched at around 108.33% of the output voltage,
while the LATSD is latched at a higher fixed voltage, around
4.19V and above the maximum BDAC output voltage. The
master over-voltage monitoring circuit is designed with the
bandgap reference of the ISL6551, rather than the ISL6550
internal reference that is used for the local over-voltage
setpoint, about 108.33% of the BDAC voltage. Thus, the
converter can gain additional protection against the failure of
the ISL6550 internal reference or mis-configuration of the
FIGURE 38. OUTPUT UNDER-VOLTAGE DELAY. CHANNEL 1:
FIGURE 39. OUTPUT UNDER-VOLTAGE DELAY. CHANNEL 1:
UVDLY; CHANNEL 2: START SIGNAL; CHANNEL
3: OUTPUT VOLTAGE
UVDLY; CHANNEL 2: START SIGNAL;
CHANNEL 3: OUTPUT VOLTAGE