ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 17

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

Special Notes for Configuring the ISL6551
The controller can be easily configured using Table 1 in the
ISL6551 datasheet. In this section, several things that
require the users’ attention are highlighted. For a detailed
configuration, please refer to the device datasheet.
• For a tighter tolerance of operating frequency, a 5% NPO
• The resonant delay should not be too long, otherwise, the
• The amount of slope contributed by the magnetizing
• The voltage at ISENSE pin should be scaled appropriately
• The peak current limit set by the PKILIM is lower than the
• The voltage at EANI and EAO should be designed lower
Sin
Sm
ceramic capacitor is recommended for CT.
residual resonant current will flow through the body diode
of the lower FET and additional losses are generated. The
maximum available duty cycle will also be decreased.
current is given by EQ. 58, while the amount of slope
contributed by the internal circuit of the IC is given by
EQ. 59. The overall slope added to the current ramp signal
is the sum of these two equations. An internal ramp
(programmed by a R_RA resistor) might not be required if
the ramp contributed by the Lmag is enough for the slope
compensation.
such that the desired peak current equals or less than
Vclamp-200mV-Vramp, as defined in EQ. 60. In addition,
the turns ratio of the current transformer, Ncs, should be
selected so that power losses at Rcs (current sense
resistor) at the lowest line and the maximum output load is
less than the power rating of one or two SMT0805
resistors so that minimum losses are induced by the Rcs
and less board space is required.
cycle-by-cycle current limit controlled by the Vclamp in the
reference design for two reasons: 1) ISENSE (at full load)
has to be designed no greater than the minimum
reference voltage (2.64V) at EANI pin, otherwise, the
monotonic output startup at full load cannot be achieved;
and 2) high losses can be introduced if ISENSE (at full
load) is pushed up to the Vclamp (3.75V) with a low turns
ratio (150:1) current transformer. In the reference design,
the ISL6550 would latch the ISL6551 off in overload
conditions.
than the Vclamp, otherwise the output will be regulated at
Vclamp and the output load will be limited to the
equivalent current voltage. Since both EANI and EAO are
clamped by the same voltage (Vclamp), the output voltage
would dip if the current ramp exceeds the EAO during the
Rcs
=
=
≤
BGREF
--------------------- -
--------------- - Rcs
Lmag
(
------------------------------------------------------------------------------ -
R RA
Vclamp 200mV
Vin
¬
•
---------- -
Ncs
•
–
Ipripeak
----------------------- -
----------------------------- -
500 10
Ncs
⋅
1
–
)
12
–
Sin D
------------------ -
Fclock
17
•
Application Note 1002
(EQ. 58)
(EQ. 59)
(EQ. 60)
• The BGREF should be kept as clean as possible,
• The SHARE pin requires a 30kΩ load. A low ESR 0.1uF or
• It is critical that the input signal to ISENSE decays to zero
Layout Considerations
• When doing the layout, users should pay special attention
startup, especially for applications with constant current
load. Hence, the EANI should be set higher than EAO,
otherwise, the output voltage cannot have a monotonic
startup. (This problem could be solved by setting the soft
start at the EANI pin instead of the CSS pin allowing the
clamping voltage to come up at a very high speed.) In the
reference design, the synchronous FETs are turned off
during start up achieving monotonic rise for resistive load
applications. The FETs are turned on after a certain load
and then cannot be turned off even back to no-load, which
achieves a better dynamic performance. Users however
can completely remove the current peak detecting circuits
(D23..., they are only handy circuits for users to turned off
the synchronous FETs whenever necessary) and rely on
the R134 and C132 to achieve monotonicity for the output
voltage startup.
otherwise, the over current trip point set at the PKILIM
would be lower than is expected due to the noise/ripple at
the bandgap reference. A low ESR 0.1uF ceramic
capacitor is recommended for decoupling. Due to an
internal race condition, the ISL6551 cannot work properly
without a 399kW resistor connecting between BGREF and
VDD pins. For additional reference load (no more than
1mA), this pull-up resistor should be scaled accordingly
such that the converter can start up properly. In other
words, VDD should source at least the amount of BGREF
external load current through the pull-up resistor.
higher ceramic capacitor should be connected to the
CS_COMP pin to design a much lower current loop
bandwidth than that of the voltage regulation loop in
current share operation.
prior to or during the clock dead time, otherwise, it could
cause severe errors in the signal reaching the PWM
comparator. Examine the current ramp tail of the converter
at maximum duty cycle and full load operations, and
extend the dead time to reset the current ramp tail if
oscillations occur. The C61 in the peak current detecting
circuits (page 6 of the schematics) causes a tail at the
current ramp. If it is removed, a smaller dead time can be
used while maintaining proper operations.
to the VSS and PGND returns (Analog Ground and Power
Ground). VSS is the reference ground, the return of VDD,
of all control circuits and must be kept as clean as possible
from all switching noises. It should be connected to the
PGND in only one location as close to the IC as practical.
For a secondary control system, it should be connected to
the net after the output capacitors, i.e., the output return
pinouts. For a primary control system, it should be