ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 14

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

The freewheeling current flows through the channel and the
body diode of upper FETs in alternate freewheeling periods
and at alternate directions. The RMS current through the
channel can be calculated with EQ. 36. The average current
through the body diode of the upper FET can be estimated
with EQ. 37.
Iprirmsfr
Thus, the overall RMS current through the channel of each
upper FET is defined in EQ. 38:
With all the above RMS and average current information, the
conduction losses of each power switch can be roughly
estimated with EQs. 39 and 40. As shown in EQs. 34 and 36,
the higher the inductor ripple current and the magnetizing
current are, i.e., the lower the output inductance and the
magnetizing inductance are, the larger the RMS currents
are, the higher the power losses would be induced by the
primary switches.
Four 100V Siliconix SUD40N10 MOSFETs are selected for
the bridge switches such that the ratings of the device are
greater than Pupfet, Plowfet, and the maximum input
voltage. Note that any switching losses, which will be
discussed later, should be included in EQs. 39 and 40 to
define the maximum power dissipation of the primary
switches, which limits the MOSFET selection.
Input Filter Design
The input pulsating current filtered by the input capacitors
has an RMS value in EQ. 41, while the minimum required
input capacitance is defined in EQ. 42.
The dV
contributed by the amount of input capacitance, of which is
the input capacitors (ITW Patron capacitors in the reference
design) that filter most of pulsating currents. The maximum
value of EQ. 41 happens at D~0.5, while the maximum value
Ipriavgfr
Pupfet
Plowfet
Cin
Iprirms
Iinrms
=
------- -
2N
IN
Io
=
=
=
=
cap is the acceptable input ripple voltage
=
=
Iprirms
•
Iprirmstr




(
Iprirmstr
------- -
2N
D D
------- -
2N
Io


Io


–
------- -
2N


Io
+
2
2
Imag
------------- -
2
•
+
•
)
(
2
2
•
-------------------------- -
2N 2 D
Rdsonpri
D D
2
•
----------------------- -
dVincap
–
+
Rdsonpri
(
–
dI
Iprirmsfr
-------------------------- -
2N 2 D
T
2
–
)
+
(
)
dI
14
(
---------------- - D
+
+
dIp
–
12
Imag
------------- -
Ipriavgfr Vd
+
2
)
2
)


2
Ipriavgres Vd
•
•


1 D
------------ -
2
–
2
+
•
------------------------------------
12N
dI
2
2
(
•
1 D
(
2 D
–
–
Application Note 1002
)
2
)
(EQ. 36)
(EQ. 37)
2
(EQ. 38)
(EQ. 39)
(EQ. 40)
(EQ. 41)
(EQ. 42)


•
1 D
------------ -
–
2
of EQ. 42 happens at D=0.5. Several lower-profile ITW
Paktron capacitors (105K100ST2814) and an external
capacitor have been used in the evaluation board. If a hold
up time (t
momentarily disconnected, then EQ. 43 helps define the
required hold up capacitance:
The overall input voltage ripple induced by the ESR and
capacitance of the input capacitors can be estimated with
EQ. 44. In addition, the spikes caused by the ESL of the
input capacitors should be decoupled with lower ESL
ceramic capacitor.
Furthermore, for a low EMI level performance, an additional
L-C filter might be required in the front end. However, the
combination of both ZVS full bridge and current doubler
topologies helps reduce the size of this input EMI filter.
Switches Losses and Driver Losses
In general, switching losses are an insignificant portion
compared to conduction losses of the power switches if ZVS
transitions are achieved. Since the commutating inductances
store the peak energy to swing the output capacitance of the
upper FET from V
freewheeling period before the upper FET is turned on,
therefore, the upper FETs are lossless at turn on transitions.
At the end of freewheeling period, the commutating
inductances store the least energy, which might not be
enough (especially in high line and/or low load conditions) to
swing the output capacitance of the lower FET to zero volt
before they are turned on. The turn-on losses of the lower
FETs can be approximated with EQ. 45. The turn-off losses
of primary switches can be minimized with a high speed
driver such as Intersil HIP2100.
When the lower FET is turned off, its corresponding upper
FET is clamped to V
corresponding synchronous FET is turned on when the
voltage across the secondary winding vanishes, therefore,
there are no turn-on switching losses for the synchronous
FETs. The resonant delay and the delay caused by the
leakage inductance to have any voltage across the
Ppriswon
Vinripple
Cin
or
where
=
--------------------------------------------------------------- -
η
HOLDUP
•
=
=
(
2Po t
Vin
1
-- - V
2
------- -
2N
Io
Cin
2
on
•
•
–
η
∆
≈
(
) is required when the input line is
HOLDUP
IN
V
•
Vin
D D
=
Po t
-------------------------------------- -
2
η Vin ∆Vin
I
on
–
IN
HOLDUP
to zero volt at the beginning of the
•
Efficiency
•
=
•
in a very short time. The
2
t
HOLDUP
Vin V
)
on
•
•
---------
Cin
•
–
T
)
Fsw
+
HOLDUP
ESRin Ipripeak
•
(EQ. 43)
(EQ. 44)
(EQ. 45)