ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 19

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

(around 70mS), then the START will not be latched. The
latch can be reset by the PEN signal, which is controlled by
the input voltage, the mechanical switch, and the thermal
condition of the converter. If latching the converter off in
overload conditions is not allowed, then version B of ISL6550
can be used. Then the converter would be running in hiccup
mode in overload conditions.
OUPUT UV & LOCAL OV (4): If the output voltage is beyond
+/-8.33% of the set point and does not reach the master OV
setpoint (4.19V) for any reason, the START is then latched,
so is the converter. The latch can be reset by the PEN.
OUPTUT MASTER OV (5): If the master OV circuit is
triggered, the LATSD is pulled high and latches the controller
off. The latch can be reset ONLY by cycling VDD. It CANNOT
be reset by toggling ENABLE (PEN).
RESET LATCH (6): The soft start capacitor starts to be
charged after the VDD increases above the ISL6551 and
ISL6550 turn-on thresholds.
VDD UV LOCKOUT (7): The IC is turned off when the VDD
is below the ISL6551 and ISL6550 turn-off thresholds. The
soft start is reset.
INPUT UV LOCKOUT (8): When the input voltage is below
its turn-off threshold 33.3V, the converter is disabled and
latched off. The soft start is reset.
Summary of Design
Table 1 is the BDAC output programming code.
10
11
12
13
14
15
16
#
0
1
2
3
4
5
6
7
8
9
TABLE 1. BDAC OUTPUT PROGRAMMING CODE
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
19
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
OUT
Application Note 1002
2.642
2.674
2.706
2.738
2.770
2.801
2.833
2.865
2.897
2.929
2.961
2.993
3.025
3.057
3.089
3.121
3.153
(V)
Table 2 summarizes major design parameter requirements.
Most components are selected or designed based on these
values. Users should generate a similar table for their
applications and select components with derating guideline
of the datasheet or their own companies.
PARAMETER
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
#
Iindpeak
Dmaxav
Iindrms
Iinrms
TABLE 1. BDAC OUTPUT PROGRAMMING CODE
Iorms
ESR
Fsw
Cin
dIo
Co
dI
TABLE 2. DESIGN PARAMETER REQUIREMENTS
VID4
DUTY CYCLE AND SWITCHING FREQUENCY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
assuming the load evenly distributed
assuming the load evenly distributed
VID3
dVtr = 150mV @ 25% Load Step
t
Lo=0.8uH, Vin=75V, Vo=3.63V
Lo=0.8uH, Vin=75V, Vo=3.63V
DEAD
between both output inductors
between both output inductors
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
Vin=75V, Lo=8uH, Vo=3.63V
Io=60A, Vin=75V, Vo=3.63V
Io=60A, Vin=75V, Vo=3.63V
Vin=48V, D~0.5, Vo=3.63V
OUTPUT CAPACITORS
OUTPUT INDUCTORS
INPUT CAPACITORS
D=0.5, dVincap=1.65V
f
=200ns, t
c
=Fsw/10=23.5kHz
VID2
Fsw=250kHz
CONDITION
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
CT=180pF
RESDLY
VID1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
=100ns,
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V
OUT
3.185
3.216
3.248
3.280
3.312
3.344
3.376
3.408
3.440
3.472
3.504
3.536
3.568
3.599
3.631
VALUE UNIT
12.9
16.3
38.2
34.7
677
235
5.4
3.4
85
10
3
(V)
kHz
mΩ
uF
uF
%
A
A
A
A
A
A