ISL6551EVAL1 Intersil, ISL6551EVAL1 Datasheet - Page 13

• Manufacturer Part Number: ISL6551EVAL1
• Description: EVALUATION BOARD ISL6551
• Manufacturer: Intersil

Specifications of ISL6551EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 60A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 470kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6551
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

current. The peak current through the FET is defined by the
load current plus half of the output ripple current in EQ. 24.
In this period, the RMS current through each FET can be
calculated with EQ. 25 using Case 2 formula. Note that the
duty cycle (D) is defined as the ratio of the ON-time interval
of a lower FET over one clock period (twice of the switching
period), which explains the 1/2 factor in the equation.
In the worst case, all the load current flows through one of
the synchronous FETs during the freewheeling period
(including the resonant and dead periods for simplicity), the
RMS current through the FET can be estimated by EQ. 26.
Thus, the overall RMS current through one synchronous
FET can be defined in EQ. 27, while the conduction losses
of each synchronous FET can be calculated with EQ. 28.
As shown in EQs. 25 and 26, the higher the ripple current is,
i.e., the lower the output inductances are, the higher the
RMS currents are, and the higher the conduction losses of
the synchronous FETs are.
In addition, the distribution factor (F
currents during the freewheeling period for the INV_LOW
DRIVE scheme can be included in EQ. 26 for an accurate
calculation:
where p is the percentage of load current through one of the
synchronous FETs. A guess of p can made by looking at the
primary freewheeling current, as shown in the
EXPERIMENTAL RESULTS section. For the other two drive
schemes, F
In the SYNC DRIVE scheme, both synchronous FETs are
turned off during the dead time period. The freewheeling
CASE 4
Isynrmsfr
F
Irms4
WHERE
Isynpeak
Isynrmstr
Psynfet
Isynrms
DIST
=
=
0
=
=


=
(
=
=
Isynrms
DIST
1 p
Ic
I ∆
Io
Ic
–
Isysrmstr
2




+
+
Io
Io
=
)
∆
------- -
2
is one.
dIo
-------- -
12
2
2
2
I
Ia
---------------- -
+
2
+
+


2
p
+
2
dIo
----------- -
dIo
----------- -
•
•
2
1 d
12
12
Ib
(
Rdsonsyn
–
2
Ib
1 d
2
2
+




–
•
Isysrmsfr
•
)
Id
1 D
------------ -
D
--- -
2
13
–
2
Ia
=
Ic d
•
DIST
2
) for IQ1 and IQ2
I ∆
=
Ib Ia
–
Application Note 1002
(EQ. 29)
(EQ. 27)
(EQ. 28)
(EQ. 26)
(EQ. 24)
(EQ. 25)
Ic
current flows through the body diodes of the FETs, and any
external schottky diodes. In the worst case, the freewheeling
current flows through only one leg, and the average current
for the dead time can be estimated by EQ. 30, where t
is the dead time and t
An additional term “Isyndeadavg x Vdsyn” should be added
to EQ. 28 if the SYNC DRIVE scheme is implemented.
Isynrmsfr however would be slightly smaller.
The maximum voltage across the synchronous FET can be
approximated with EQ. 31, adding 30% margin for the
ringing on the rising edge.
The synchronous FETs should be selected such that the
V
than Vsynmax and Psynfet, respectively. Four 30V Siliconix
Si4842DY MOSFETs are used for each leg. Note that any
switching losses, which will be discussed later, should be
included in the calculation to define the maximum power
dissipation.
Calculations for Primary Switches
(QA, QB, QC, & QD)
The peak current through the primary winding happens at
the end of the active period, as defined in EQ. 32
EQ. 33 defines the peak-to-peak magnetizing current. The
RMS current through the power switches in the active period
can be estimated by EQ. 34, which also defines the overall
RMS current through a lower FET.
If there is a time delay Td to turn on the lower FET after its
output capacitance is completely discharged, i.e, the
resonant delay is set longer than is necessary, then the
current will flow through the body diode of the lower FET,
which has an average value defined in EQ. 35.
Ipriavgres
Isyndeadavg
Vsynmax
Iprirmstr
Imag
Ipripeak
DS
where
rating and power rating of the MOSFETs are greater
=
(
----------------------------------------------------------------------------- -
Vin 2 I • p Rdsonpri
=
=
=
=
Io
---------------- -
Vinmax
--------------------- - 1
–
2N




=
+
dIp


------- -
2N
Lmag Fclock
Io
------- -
2N
N
Io
dI
t
---------------- - Io
DEAD
4 T
+


+
=
•
2
Imag
------------- -
Imag
------------- -
•
(
+
dI
---- -
•
N
RESDLY
2
2
dIp
----------- -


+
+
12
0.3
Imag
+
2
+


dI D
----------------------------------- -
)
dIo t
---------------------------------------------------------------------------------------------------- -
•
2N 2 D
(
D
--- -
2
is the resonant time.
) D
(
(
+
•
DEAD
Td T ⁄
–
)
+
)


t
(
RESDLY
•
1 D
Td
------ -
2T
–
) T
•
–
0.5T 1 D
(EQ. 30)
(EQ. 31)
(EQ. 32)
(EQ. 33)
(EQ. 34)
(EQ. 35)
DEAD
(
–
)
)

