SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 103
SW-QUARTUS-SE-FIX
Manufacturer Part Number
SW-QUARTUS-SE-FIX
Description
QUARTUS II ANNUAL SUBSCRIPTION
Manufacturer
Altera
Type
Design Softwarer
Series
QUARTUS IIr
Specifications of SW-QUARTUS-SE-FIX
Mfg Application Notes
Software Licensing App Note
Core Architecture
CPLD, FPGA
Supported Families
Quartus II, Nios II
Software Edition
Standard
License Type
Fixed - Node
Supported Hosts
Windows
Rohs Compliant
NA
For Use With/related Products
Altera Devices
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1247
FIXEDPC
FIXEDPC
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
SW-QUARTUS-SE-FIX
Manufacturer:
Altera
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C
U
Using SignalProbe
Using the In-System Memory
Content Editor
94
SING
HAPTER
f
S
■
IGNAL
7: D
I
NTRODUCTION TO THE
P
ROBE
EBUGGING AND
The SignalProbe feature allows you to route user-specified signals to output
pins without affecting the existing fitting in a design, so that you can debug
signals without having to recompile the design. Starting with a fully routed
design, you can select and route signals for debugging through I/O pins that
were either previously reserved or are currently unused.
The SignalProbe feature allows you to specify which signals in the design to
debug, perform a SignalProbe compilation that connects those signals to
unused or reserved output pins, and then send the signals to an external
logic analyzer. You can use the Node Finder when assigning pins to find the
available SignalProbe sources. A SignalProbe compilation typically takes
approximately 20% to 30% of the time required for a standard compilation.
You can use the SignalProbe feature with Tcl. With Tcl commands, you can
add and remove SignalProbe assignments and sources, perform a
SignalProbe compilation on a design, and compile routed SignalProbe
signals in a full compilation.
The In-System Memory Content Editor allows you to view and modify, at
run-time, RAM, ROM, or register content independently of the system clock
of a design. You analyze design memory with the In-System Memory
Content Editor through a JTAG interface using standard programming
hardware.
For Information About
Using the SignalProbe feature
E
NGINEERING
Q
UARTUS
C
II S
HANGE
OFTWARE
M
ANAGMENT
Refer To
Quick Design Debugging Using SignalProbe
chapter in volume 3 of the Quartus II
Handbook
“About SignalProbe” in Quartus II Help
A
LTERA
C
ORPORATION
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