SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 4

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

Contents
Preface ............................................................................................................................................vii
Chapter 1: Design Flow.................................................................................................................. 1
Chapter 2: Design Entry............................................................................................................... 19
Chapter 3: Synthesis ..................................................................................................................... 39
A
LTERA
C
Introduction....................................................................................................................... 2
Graphical User Interface Design Flow .......................................................................... 3
Command-Line Executables ........................................................................................... 7
Design Methodologies and Planning .......................................................................... 14
Introduction..................................................................................................................... 20
Creating a Project............................................................................................................ 21
Creating a Design ........................................................................................................... 22
Using Altera Megafunctions......................................................................................... 24
Constraint Entry ............................................................................................................. 31
Introduction..................................................................................................................... 40
Using Quartus II Verilog HDL & VHDL Integrated Synthesis................................ 41
Using the Design Assistant to Check Design Reliability .......................................... 44
Analyzing Synthesis Results With the Netlist Viewers ............................................ 45
ORPORATION
Using Standard Command-Line Commands & Scripts ............................. 10
Using Tcl Commands ...................................................................................... 12
Incremental Design Flows .............................................................................. 14
Using LogicLock Regions ............................................................................... 15
Using LogicLock Regions in Incremental Compilation Flows.................. 16
Using the Quartus II Block Editor ................................................................. 22
Using the Quartus II Symbol Editor.............................................................. 22
Using the Quartus II Text Editor.................................................................... 23
Using Verilog HDL, VHDL, & AHDL........................................................... 23
Using the State Machine Editor ..................................................................... 24
Using Intellectual Property (IP) Megafunctions.......................................... 25
Using the MegaWizard Plug-In Manager..................................................... 27
Instantiating Megafunctions in the Quartus II Software............................ 27
Instantiating Megafunctions in EDA Tools .................................................. 28
Using the Assignment Editor ......................................................................... 32
Using the Pin Planner...................................................................................... 33
The Settings Dialog Box .................................................................................. 35
Making Timing Constraints............................................................................ 36
Creating Design Partitions.............................................................................. 36
Creating Design Partitions with the Design Partitions Planner................ 37
Using Quartus II Synthesis Netlist Optimization Options ........................ 43
Instantiation in Verilog HDL & VHDL........................................... 28
Using the Port & Parameter Definition .......................................... 28
Inferring Megafunctions................................................................... 28
Using the Black Box Methodology.................................................. 29
Instantiation by Inference................................................................. 29
Using the Clear Box Methodology.................................................. 29
I
NTRODUCTION TO THE
Q
UARTUS
II S
OFTWARE
■
III