SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 115

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

C
I
Introduction
Figure 1. EDA Tool Design Flow
106
NTRODUCTION
HAPTER
Timing Analysis
Quartus II
■
8: EDA T
I
NTRODUCTION TO THE
The Quartus II software allows you to use the EDA tools you are familiar
with for various stages of the design flow, including synthesis, simulation,
and formal verification.
The following steps describe the basic design flow for using other EDA tools
with the Quartus II software:
1.
OOL
Create a new project and specify a target device or device family.
Quartus II Fitter
S
Analysis &
Assembler
Quartus II
Quartus II
Synthesis
UPPORT
Q
EDA Netlist Writer
UARTUS
Quartus II
Figure 1
Programmer
Quartus II
II S
Source design files
including VHDL Design
Files (.vhd) & Verilog
Design Files (.v)
OFTWARE
EDIF netlist
files (.edf) or Verilog
Quartus Mapping Files (.vqm)
Output files for EDA tools
including Verilog Output Files
(.vo), VHDL Output Files (.vho),
VQM Files, Standard Delay Format
Output Files (.sdo), testbench
files, symbol files, Tcl script files
(.tcl), IBIS Output Files (.ibs),
HSPICE Simulation Deck Files
(.sp), and STAMP model files
(.data, or .mod)
shows the EDA tool design flow.
EDA Synthesis
Tool
A
LTERA
Formal Verification
Timing Analysis
EDA Simulation
Synthesis Tool
Design Tools
EDA Physical
Board Level
C
Tools
Tools
Tools
ORPORATION
EDA
EDA
EDA