SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 51

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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NTRODUCTION TO THE
YNTHESIS
II V
If your design instantiates Altera megafunctions, library of parameterized
modules (LPM) functions, or intellectual property (IP) megafunctions in a
third-party EDA tool, you need to use a hollow-body or black box file. When
you are instantiating megafunctions for Quartus II Analysis & Synthesis,
however, you can instantiate the megafunction directly without using a
black box file. For more information about instantiating megafunctions,
refer to
and
“Design Entry.”
Analysis & Synthesis builds a single project database that integrates all the
design files in a design entity or project hierarchy. The Quartus II software
uses this database for the remainder of project processing. Other Compiler
modules update the database until it contains the fully optimized project. In
the beginning, the database contains only the original netlists; at the end, it
contains a fully optimized, fitted project, which is used to create one or more
files for timing simulation, timing analysis, and device programming.
As it creates the database, the analysis stage of Analysis & Synthesis
examines the logical completeness and consistency of the project, and checks
for boundary connectivity and syntax errors. Analysis & Synthesis also
synthesizes and performs technology mapping on the logic in the design
entity or project’s files. It infers flipflops, latches, and state machines from
Verilog HDL and VHDL. It creates state assignments for state machines and
makes choices that minimize resources usage.
Analysis & Synthesis uses several algorithms to minimize gate count,
remove redundant logic, and utilize the device architecture as efficiently as
possible. You can customize synthesis by using logic option assignments.
Analysis & Synthesis also applies logic synthesis techniques to help
implement timing requirements for a project and optimize the design to
meet these requirements. Quartus II logic options allow you to set attributes
without editing the source code. You can assign individual Quartus II logic
options in the Assignment Editor, and you can specify global Analysis &
Synthesis logic options for the project in the Analysis & Synthesis Settings
page of the Settings dialog box.
For Information About
Quartus II Verilog HDL and VHDL
Synthesis support
ERILOG
“Instantiating Megafunctions in EDA Tools” on page 28 in Chapter 2,
“Instantiating Megafunctions in the Quartus II Software” on page 27
HDL & VHDL I
Q
UARTUS
NTEGRATED
II S
OFTWARE
S
YNTHESIS
Refer To
“Quartus II Verilog HDL Support,”
“Quartus II VHDL Support,” and “Quartus II
Support for SystemVerilog 2005” in
Quartus II Help
A
LTERA
C
ORPORATION