SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 120

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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Writer on the Processing menu. If you are using the NativeLink feature, you
can also run a simulation after an initial compilation with the Run EDA
Simulation Tool command on the Tools menu.
The Quartus II software also allows you to generate the following types of
output files for use in performing functional and timing simulation in EDA
simulation tools:
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Simulation Libraries
Altera provides functional simulation libraries for designs that contain
Altera-specific components, and atom-based timing simulation libraries for
designs compiled in the Quartus II software. You can use these libraries to
perform functional or timing simulation of any design with Altera-specific
components in EDA simulation tools that are supported by the Quartus II
software. Additionally, Altera provides pre-compiled functional and timing
simulation libraries for simulation in the ModelSim-Altera software.
Altera provides functional simulation libraries for designs that use Altera
megafunctions and standard library of parameterized modules (LPM)
functions. Altera also provides pre-compiled versions of the altera_mf and
220model libraries for simulation in the ModelSim software.
Test Bench Files: You can create Verilog Test Bench Files (.vt) and
VHDL Test Bench Files (.vht) for use with EDA simulation tools from a
Vector Waveform File (.vwf) in the Quartus II Waveform Editor, using
the Export command on the File menu. Verilog HDL and VHDL Test
Bench Files are test bench template files that contain an instantiation of
the top-level design file and test vectors from the Vector Waveform File.
You can also generate self-checking test bench files if you specify the
expected values in the Vector Waveform File.
Memory Initialization Files: You can use the Quartus II Memory
Editor to enter the initial contents of a memory block, for example,
content-addressable memory (CAM), RAM, or ROM, in a Memory
Initialization File (.mif) or a Hexadecimal (Intel-Format) File (.hex).
Signal Activity Files: You can create Signal Activity Files for use with
the PowerPlay Power Analyzer. A Signal Activity File contains toggle
rate and static probability data for a design. You can specify a limit for
the signal activity period, and can also specify that glitch filtering can
be performed.
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