SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 77

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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UNNING THE
HAPTER
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5: T
I
NTRODUCTION TO THE
T
IME
IMING
The TimeQuest analyzer reports results only when requested. You can
customize each report on demand to display specific timing information.
Specifying Timing Constraints
You can make individual timing constraints for individual entities, nodes,
and pins with the Constraints menu of the TimeQuest analyzer. Individual
timing assignments override project-wide requirements. You can also
asssign timing exceptions to nodes and paths to avoid reporting of incorrect
or irrelevant timing violations. The TimeQuest analyzer supports
point-to-point timing constraints, wildcards to identify specific nodes when
making constraints, and assignment groups to make individual constraints
to groups of nodes.
You can make the following types of individual timing assignments in the
TimeQuest analyzer:
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You can make the following types of individual timing exceptions as
assignments in the TimeQuest analyzer:
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Q
UEST
Clock settings—Allow you to perform an accurate multiclock timing
analysis by defining the timing requirements and relationship of all
clock signals in the design. The TimeQuest analyzer supports both
single-clock and multiclock frequency analysis.
Clock uncertainty assignments—Allow you to specify the expected
clock setup or hold uncertainty (jitter) that should be used when
performing setup and hold checks. The TimeQuest analyzer subtracts
the specified setup uncertainty from the data required time when
calculating setup checks and adds the specified hold uncertainty to the
data required time when calculating hold checks.
Input and Output Delays—Allow you to specify external device or
board timing parameters by specifying the required data arrival times
at specified input and output ports relative to the clock.
Multicycle paths—Paths between registers that require more than one
clock cycle to become stable. You can set multicycle paths to instruct the
analyzer to relax its measurements and avoid incorrect setup or hold
time violations.
False paths—You can designate as false paths any paths in the design
which the timing analyzer disregards during analysis and reporting. By
default, the Quartus II software cuts (directs the timing analyzer to
A
NALYSIS AND
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IMING
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NALYZER
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PTIMIZATION
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LTERA
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ORPORATION