SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 67

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

C
O
Optimizing the Fit
58
HAPTER
PTIMIZING THE
f
■
4: P
I
NTRODUCTION TO THE
LACE AND
F
You can view the routing congestion in a design, view routing delay
information for paths, and view connection counts to specific nodes. The
Chip Planner also allows you to view the node fan-out and fan-in for specific
structures, or view the paths between specific nodes. If necessary, you can
change or delete resource assignments.
Using the Design Assistant to Check
Design Reliability
The Quartus II Design Assistant allows you to check the reliability of your
design, based on a set of design rules, to determine whether there are any
issues that may affect fitting or design optimization. The Design Assistant
page of the Settings dialog box allows you to specify which design reliability
guidelines to use when checking your design.
Once you have run the Fitter and have analyzed the results, you can try
several options to optimize the fit:
■
■
■
■
Using Location Assignments
You can assign logic to physical resources on the device, such as a pin, logic
cell, or Logic Array Block (LAB), by using the Chip Planner or the
Assignment Editor in order to control place and route. You may want to use
the Chip Planner to edit assignments because it gives you a graphical view
IT
For Information About
Viewing the fit in the Chip Planner
Using location assignments
Setting options that control place and route
Using the Resource Optimization Advisor
Using the Design Space Explorer
R
OUTE
Q
UARTUS
II S
OFTWARE
Refer To
Engineering Change Management with the
Chip Planner chapter in volume 3 of the
Quartus II Handbook
A
LTERA
C
ORPORATION