SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 45

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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ONSTRAINT
HAPTER
f
■
2: D
I
NTRODUCTION TO THE
E
NTRY
ESIGN
■
Making Timing Constraints
The TimeQuest Timing Analyzer accepts constraints in Synopsys Design
Constraint format to define the parameters for analysis. You can make
timing constraints using the commands in the TimeQuest Timing Analyzer
GUI or equivalent Tcl commands. For more information on the TimeQuest
Timing Analyzer, refer to
Optimization” on page
Creating Design Partitions
You can designate separate hierarchical sections of your design as design
partitions to compile incrementally, without affecting the rest of the project.
The Project Navigator, the Design Partition Planner, and the Design
Partitions window allow you to assign design partitions.
To make a LogicLock assignment for a partition, drag the partition from the
Project Navigator window directly to the LogicLock Regions window or to
a LogicLock region in the Timing Closure Floorplan. You can also right-click
the partition/entity in the Project Navigator, point to LogicLock Region,
and then click Create New LogicLock Region.
To specify an entity as a design partition, on the Assignments menu, click
Design Partitions Window.
The Design Partitions window allows you to specify one of the following
options for Netlist Type:
■
■
For Information About
Assigning project-wide settings with
the Settings dialog box
Specify Design Assistant and SignalTap II settings: enable the Design
Assistant and enable the SignalTap II Logic Analyzer; specify a
SignalTap II File (.stp) name.
Source File—directs the Compiler to compile from source design files
Post-Synthesis—preserves synthesis results for the partition (default
option for new partitions)
E
NTRY
Q
UARTUS
65.
“Chapter 5: Timing Analysis and Design
II S
OFTWARE
Refer To
“Module 3: Compile a Design” in the
Quartus II Interactive Tutorial
A
LTERA
C
ORPORATION