SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 81

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

C
R
72
UNNING THE
HAPTER
■
5: T
I
NTRODUCTION TO THE
T
IME
IMING
Viewing Timing Delays with the
Technology Map Viewer
The Quartus II Technology Map Viewer provides a low-level, or atom-level,
technology-specific schematic representation a design. The Technology Map
Viewer includes a schematic view, and also includes a hierarchy list, which
lists the instances, primitives, pins, and nets for the entire design netlist.
After performing timing analysis, or performing a full compilation that
includes timing analysis, you can use the Technology Map Viewer to view
the nodes that make up a timing path, including information about total
delay and individual node delay
To view timing information in the Technology Map Viewer, right-click path
information in a timing analyzer report, and then click Locate Path. In the
Locate dialog box, under Locate in, select Technology Map Viewer.
Figure 4. Technology Map View Window—Delay Information
Q
UEST
A
NALYSIS AND
T
IMING
A
Total delay information
NALYZER
Q
D
UARTUS
ESIGN
O
II S
PTIMIZATION
OFTWARE
(Figure
4).
Individual delay information
A
LTERA
C
ORPORATION