SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 83

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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IMING
HAPTER
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LOSURE
5: T
I
NTRODUCTION TO THE
IMING
Using the Chip Planner
You can use the Chip Planner to view logic placement made by the Fitter,
view user assignments and LogicLock region assignments, and routing
information for a design. You can use this information to identify critical
paths in the design and make timing assignments, location assignments, and
LogicLock region assignments to achieve timing closure.
Chip Planner Tasks And Layers
The Chip Planner can simultaneously show user assignments and Fitter
location assignments. You can customize the way the Chip Planner displays
information with the Task list and the commands the View menu.
The following are the pre-defined tasks in the Chip Planner:
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You can use the Layers Settings command on the View menu to select more
than one combination of these elements for a customized view of your
design in the device. You can view global and local routing, ports, used and
unused assignments, pin and location assignments, user and fitter-placed
LogicLock regions, clock regions, and other elements in any combination.
Making Assignments
To facilitate achieving timing closure, the Chip Editor assignment tasks
allow you to make or change location assignments directly in the floorplan.
You can create and assign nodes or entities to custom regions and to
LogicLock regions, and you can also edit existing assignments to logic cells,
rows, columns, and regions.. You can also locate any node (or set of nodes)
and make assignments in the Assignment Editor.
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The Quartus II Chip Planner provides a single interface for viewing and making
changes to the design floorplan as well as making ECO-style post-fit netlist changes.
For the list of devices supported by Chip Planner, see Quartus II Help.
Floorplan editing
Post-compilation editing
Partition display
Clock region assignment creation
A
NALYSIS AND
Using Chip Planner to Achieve Timing Closure
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UARTUS
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PTIMIZATION
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