SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 15

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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HAPTER
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1: D
U
I
NTRODUCTION TO THE
SER
ESIGN
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I
NTERFACE
(Optional) Perform an early timing estimate to generate early estimates
of timing results before fitting.
Synthesize the design with Analysis & Synthesis.
(Optional) If your design contains partitions and you are not
performing a full compilation, merge the partitions with partition
merge.
(Optional) Generate a functional simulation netlist for your design and
perform a functional simulation with an EDA simulation tool.
Place and route the design with the Fitter.
Perform a power estimation and analysis with the PowerPlay Power
Analyzer.
Use an EDA simulation tool to perform timing simulation for the
design.
Use the TimeQuest Timing Analyzer to analyze the timing of your
design.
(Optional) Use physical synthesis, the Chip Planner, LogicLock
regions, and the Assignment Editor to correct timing problems.
Create programming files for your design with the Assembler, and then
program the device with the Programmer and Altera programming
hardware.
(Optional) Debug the design with the SignalTap
external logic analyzer, the SignalProbe feature, or the Chip Planner.
(Optional) Manage engineering changes with the Chip Planner, the
Resource Property Editor, or the Change Manager.
F
LOW
D
ESIGN
F
LOW
Q
UARTUS
II S
OFTWARE
®
II Logic Analyzer, an
A
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ORPORATION
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