SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 16

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

Command-Line Executables
Figure 4. Command-Line Design Flow
A
LTERA
Verilog Design Files (.v), VHDL Design Files (.vhd),
Verilog Quartus Mapping Files (.vqm), Text Design
Files (.tdf), Block Design Files (.bdf) & EDIF netlist
files (.edf)
Output files for EDA tools
including Verilog Output
Files (.vo), VHDL Output
Files (.vho), VQM Files &
Standard Delay Format
Output Files (.sdo)
C
ORPORATION
EDA Netlist Writer
Timing Analyzer
quartus_sim
quartus_eda
quartus_sta
TimeQuest
Quartus II Shell
Simulator
quartus_sh
The Quartus II software includes separate executables for each stage of the
design flow. Each executable occupies memory only while it is running. You
can use these executables with standard command-line commands and
scripts, with Tcl scripts, and in makefiles. See
command-line executables.
quartus_pgm
Programmer
I
NTRODUCTION TO THE
Programming File
quartus_map
quartus_asm
quartus_cpf
quartus_fit
Assembler
Analysis &
Converter
Synthesis
Fitter
Q
Table 2
UARTUS
C
C
Compiler Database
OMMAND
HAPTER
SignalTap II Logic
for a list of all available
Design Assistant
PowerPlay Power
II S
quartus_pow
quartus_cdb
quartus_drc
quartus_stp
Analyzer
Analyzer
OFTWARE
-L
1: D
INE
ESIGN
E
XECUTABLES
■
F
LOW
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