SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 25

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

C
D
16
HAPTER
ESIGN
f
■
M
ETHODOLOGIES AND
1: D
I
NTRODUCTION TO THE
ESIGN
After you perform analysis and elaboration or a full compilation, the
Quartus II software displays the hierarchy of the design in the Hierarchy tab
of the Project Navigator. You can click any of the design entities in this view
and create new LogicLock regions from them, or drag them into an existing
LogicLock region in the Timing Closure Floorplan.
Altera also provides LogicLock Tcl commands to assign LogicLock region
content at the command line or in the Quartus II Tcl Console window. You
can use the provided Tcl commands to create floating and auto-size
LogicLock regions, add a node or a hierarchy to a region, preserve the
hierarchy boundary, back-annotate placement results, import and export
regions, and save intermediate synthesis results.
Using LogicLock Regions in
Incremental Compilation Flows
If you are planning to perform a full incremental compilation, it is important
to assign design partitions to physical locations on the device. You can
assign design partitions to LogicLock regions by dragging a design partition
from the Hierarchy tab of the Project Navigator window, the Design
Partitions window, or the Node Finder and dropping it directly in the
LogicLock Regions window or to a LogicLock region in the Chip Planner.
Create one LogicLock region for each partition in your design. You can
achieve the best performance when these regions are all fixed-size,
fixed-location regions. Ideally, you should assign the LogicLock regions
manually to specific physical locations in the device by using the Chip
Planner; however, you can also allow the Quartus II software to assign
LogicLock regions to physical locations somewhat automatically by setting
the LogicLock region Size option to Auto and the State properties to
Floating. After the initial compilation, you should back-annotate the
LogicLock region properties (not the nodes) to ensure that all the LogicLock
regions have a fixed size and a fixed location. This process creates initial
floorplan assignments that can be modified more easily, as needed.
For Information About
Using LogicLock with the Quartus II
software
F
LOW
P
LANNING
Q
UARTUS
II S
OFTWARE
Refer To
Area and Timing Optimization chapter in
volume 2 of the Quartus II Handbook
“About LogicLock Regions” in Quartus II
Help
A
LTERA
C
ORPORATION