SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 124

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

Figure 3. Formal Verification Flow
A
LTERA
RTL VHDL & Verilog HDL source
design files compared against
Verilog Output Files (.vo) (Cadence
Encounter Conformal Only)
C
EDA Synthesis
ORPORATION
Tools
The type of formal verification supported by the Quartus II software is
equivalence checking, which compares the functional equivalence of the
source design with the revised design by using mathematical techniques
rather than by performing simulation using test vectors. Equivalence
checking greatly decreases the time to verify the design. The Quartus II
software allows you to verify the logical equivalence between the
synthesized gate-level Verilog Quartus Mapping Files (.vqm) generated by
an EDA synthesis tool and the Verilog Output Files (.vo) generated by the
Quartus II software. For the Cadence Encounter Conformal software, the
Quartus II software also allows you to verify the logical equivalence
between RTL VHDL design files (.vhd) or Verilog HDL design files (.v) and
Quartus II software–generated Verilog Output Files.
file types are compared in formal verification.
Gate-level VQM Files
compared against Quartus II
Verilog Output Files (.vo)
RTL Verilog HDL or
VHDL source design
files (.v, .vhd)
Verilog
Quartus
Mapping
Files (.vqm)
Quartus II Formal
Verification Libraries
Analysis & Synthesis
Verification Tool
quartus_map
EDA Formal
I
Quartus II
NTRODUCTION TO THE
Compared against VQM
Files or RTL source files
EDA Netlist Writer
Quartus II Fitter
quartus_eda
quartus_fit
Quartus II
Q
C
HAPTER
UARTUS
Verilog
Output
Files (.vo)
Figure 4
8: EDA T
II S
OFTWARE
F
ORMAL
shows which
OOL
Tool-specific
formal
verification
scripts
V
ERIFICATION
S
■
UPPORT
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