SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 116

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

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You can also run the EDA Netlist Writer to generate the necessary output files
separately at the command prompt or in a script by using the quartus_eda
executable. You must run the Quartus II Fitter executable quartus_fit before
running the EDA Netlist Writer.
The quartus_eda executable creates a separate text-based report file that can be
viewed with any text editor.
If you want to get help on the quartus_eda executable, type one of the following
commands at the command prompt:
quartus_eda -h
quartus_eda -help
quartus_eda --help=<topic name>
Specify which EDA design entry, synthesis, simulation, timing
analysis, board-level verification, formal verification, and physical
synthesis tools you are using with the Quartus II software, and specify
additional options for those tools.
Create a Verilog HDL or VHDL design file with a standard text editor
or use the MegaWizard Plug-In Manager to create custom variations
of megafunctions.
Synthesize your design with one of the Quartus II-supported EDA
synthesis tools, and generate an EDIF netlist file (.edf) or a Verilog
Quartus Mapping File (.vqm).
(Optional) Perform functional simulation on your design with one of
the Quartus II-supported simulation tools.
Compile your design with the Quartus II software. Run the EDA Netlist
Writer to generate output files for use with other EDA tools.
(Optional) Perform timing analysis and simulation on your design with
one of the Quartus II-supported EDA timing analysis or simulation
tools.
(Optional) Perform formal verification with one of the
Quartus II-supported EDA formal verification tools to make sure that
Quartus II post-fit netlist is equivalent to that of the synthesized netlist.
Program the device with the Programmer and Altera hardware.
Using the quartus_eda executable
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