SW-QUARTUS-SE-FIX Altera, SW-QUARTUS-SE-FIX Datasheet - Page 49

• Manufacturer Part Number: SW-QUARTUS-SE-FIX
• Description: QUARTUS II ANNUAL SUBSCRIPTION
• Manufacturer: Altera
• Type: Design Softwarer
• Series: QUARTUS IIr

Specifications of SW-QUARTUS-SE-FIX

• Mfg Application Notes: Software Licensing App Note
• Core Architecture: CPLD, FPGA
• Supported Families: Quartus II, Nios II
• Software Edition: Standard
• License Type: Fixed - Node
• Supported Hosts: Windows
• Rohs Compliant: NA
• For Use With/related Products: Altera Devices
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1247; FIXEDPC

C
I
Introduction
Figure 1. Synthesis Design Flow
40
Verilog HDL &
VHDL source design
files (.v, .vhd)
NTRODUCTION
HAPTER
■
3: S
I
NTRODUCTION TO THE
VHDL Design Files (.vhd),
Verilog HDL Design Files (.v),
Text Design Files (.tdf) & Block
Design Files (.bdf)
YNTHESIS
You can use the Analysis & Synthesis module of the Compiler to analyze
your design files and create the project database. Analysis & Synthesis uses
Quartus II Integrated Synthesis to synthesize your Verilog Design Files (.v)
or VHDL Design Files (.vhd). If you prefer, you can use other EDA synthesis
tools to synthesize your Verilog HDL or VHDL design files, and then
generate an EDIF netlist file (.edf) or a Verilog Quartus Mapping File (.vqm)
that can be used with the Quartus II software.
design flow.
You can start a full compilation in the Quartus II software, which includes
the Analysis & Synthesis module, or you can start Analysis & Synthesis
separately. You can perform an Analysis & Elaboration to check a design for
syntax and semantic errors without performing a complete Analysis &
Synthesis or use the Analyze Current File command on the Processing
menu to check a single design file for syntax errors.
For more information about starting a full compilation or starting Compiler
modules individually, refer to
page 3
Tcl Design Flows.”
EDA Synthesis
Tools
and
“Introduction” on page 38 in Chapter 3, “Command-Line And
EDIF netlist files (.edf) &
Verilog Quartus Mapping
Files (.vqm)
Q
UARTUS
II S
“Graphical User Interface Design Flow” on
Quartus II Analysis &
OFTWARE
Design Assistant
Library Mapping
Files (.lmf) &
User Libraries
quartus_drc
quartus_map
Quartus II
Synthesis
Figure 1
Compiler Database
Files (.rdb) & Report
Files (.rpt, .htm)
shows the synthesis
Netlist Viewers
A
Quartus II
LTERA
C
to Quartus II
Fitter
ORPORATION