PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet
PIC18C801-I/L
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PIC18C801-I/LR
PIC18C801I/L
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PIC18C801-I/L Summary of contents
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... Maximum Addressing Single Word (bytes) Instructions PIC18C601 256K 128K PIC18C801 2M 1M • 160 ns instruction cycle MHz clock input - 4 MHz - 6 MHz clock input with PLL active • 16-bit wide instructions, 8-bit wide data path • Priority levels for interrupts • Single Cycle Hardware Multiplier Peripheral Features: • ...
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... PIC18C601/801 Pin Diagrams 64-Pin TQFP RE1/AD9 2 RE0/AD8 3 RG0/ALE 4 RG1/OE 5 RG2/WRL 6 RG3/WRH 7 MCLR RG4/BA0 RF7/UB 12 RF6/LB 13 RF5/CS1 14 RF4/A16 15 RF3/CSIO 16 RF2/AN7 DS39541A-page 2 PIC18C601 Advance Information 48 RB0/INT0 47 RB1/INT1 46 RB2/INT2 45 RB3/CCP2 44 RB4 43 RB5 42 RB6 OSC2/CLKO 39 OSC1/CLKI RB7 36 RC5/SDO 35 RC4/SDI/SDA 34 RC3/SCK/SCL 33 RC2/CCP1 2001 Microchip Technology Inc. ...
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... Pin Diagrams (Cont.’d) 68-Pin PLCC RE1/AD9 11 RE0/AD8 12 RG0/ALE 13 RG1/OE 14 RG2/WRL 15 RG3/WRH 16 MCLR RG4/BA0 RF7/UB RF6/LB 22 RF5/CS1 23 RF4/A16 24 RF3/CSIO 25 26 RF2/AN7 2001 Microchip Technology Inc. PIC18C601/801 PIC18C601 Advance Information 60 RB0/INT0 59 RB1/INT1 58 RB2/INT2 57 RB3/CCP2 56 RB4 55 RB5 54 RB6 OSC2/CLKO 50 OSC1/CLKI RB7 47 RC5/SDO 46 RC4/SDI/SDA 45 RC3/SCK/SCL 44 RC2/CCP1 DS39541A-page 3 ...
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... RE0/AD8 4 RG0/ALE 5 RG1/OE 6 RG2/WRL 7 8 RG3/WRH 9 MCLR/V PP RG4/BA0 RF7/UB 14 RF6/LB RF5/CS1 15 16 RF4/CS2 RF3/CSIO 17 RF2/AN7 18 19 RH4/AN8 20 RH5/AN9 DS39541A-page PIC18C801 Advance Information 60 RJ5/D5 59 RJ4/D4 58 RB0/INT0 57 RB1/INT1 56 RB2/INT2 55 RB3/CCP2 RB4 54 53 RB5 RB6 OSC2/CLKO OSC1/CLKI RB7 47 46 RC5/SDO 45 RC4/SDI/SDA RC3/SCK/SCL 44 RC2/CCP1 43 RJ3/D3 ...
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... RH3/A19 RE1/AD9 14 RE0/AD8 15 RG0/ALE 16 RG1/OE 17 RG2/WRL 18 RG3/WRH 19 MCLR RG4/BA0 RF7/UB 25 RF6/LB 26 RF5/CS1 27 RF4/CS2 28 RF3/CSIO 29 RF2/AN7 30 RH4/AN8 31 RH5/AN9 2001 Microchip Technology Inc. PIC18C601/801 PIC18C801 Advance Information 75 RJ5/ RJ4/D4 RB0/INT0 72 RB1/INT1 71 RB2/INT2 70 69 RB3/CCP2 68 RB4 67 RB5 66 RB6 OSC2/CLKO 62 OSC1/CLKI RB7 59 RC5/SDO 58 RC4/SDI/SDA 57 RC3/SCK/SCL ...
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... Appendix A: Data Sheet Revision History.................................................................................................................. 303 Appendix B: Device Differences ................................................................................................................................ 303 Appendix C: Device Migrations .................................................................................................................................. 304 Appendix D: Migrating from other PICmicro Devices ................................................................................................. 304 Appendix E: Development Tool Version Requirements ............................................................................................. 305 Index ........................................................................................................................................................................... 307 On-Line Support .......................................................................................................................................................... 315 Reader Response ....................................................................................................................................................... 316 Product Identification System...................................................................................................................................... 317 DS39541A-page 6 Advance Information 2001 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2001 Microchip Technology Inc. PIC18C601/801 Advance Information DS39541A-page 7 ...
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... PIC18C601/801 NOTES: DS39541A-page 8 Advance Information 2001 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device specific information for the following two devices: 1. PIC18C601 2. PIC18C801 The PIC18C601 is available in 64-pin TQFP and 68-pin PLCC packages. The PIC18C801 is available in 80-pin TQFP and 84-pin PLCC packages. TABLE 1-1: DEVICE FEATURES Features Operating Frequency Bytes External Max ...
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... PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2 RB4 RB5 RB6 RB7 PORTC RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX1/CK1 RC7/RX1/DT1 PORTD RD7:RD0/AD7:AD0 8 PORTE 8 RE7:RE0/AD15:AD8 PORTF RF0/AN5 RF1/AN6 RF2/AN7 RF3/CSIO RF4/A16 RF5/CS1 RF6/LB RF7/UB PORTG RG0/ALE RG1/OE RG2/WRL RG3/WRH RG4/BA0 2001 Microchip Technology Inc. ...
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... FIGURE 1-2: PIC18C801 BLOCK DIAGRAM AD7:AD0 TablePointer<21> 21 inc/dec logic 21 20 PCLATU 21 Address Latch Program Memory ( Mbytes) Data Latch 16 Table Latch 8 ROM Latch A19:A16, AD15:AD0 Instruction Decode & Control OSC2/CLKO OSC1/CLKI Timing T1OSI Generation T1OSO Timer0 Timer1 CCP1 CCP2 10-bit A/D 2001 Microchip Technology Inc. ...
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... OSC1/CLKI 39 50 OSC1 CLKI OSC2/CLKO 40 51 OSC2 CLKO Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39541A-page 12 Pin Buffer PIC18C801 Type Type TQFP PLCC Description — 1, 22, — — These pins should be left 43, 64 unconnected ...
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... RA5/AN4/SS/LVDIN 27 38 RA5 AN4 SS LVDIN Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2001 Microchip Technology Inc. Pin Buffer PIC18C801 Type Type TQFP PLCC Description PORTA is a bi-directional I/O port I/O TTL I Analog 29 41 I/O TTL ...
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... RB7 37 48 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39541A-page 14 Pin Buffer PIC18C801 Type Type TQFP PLCC Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs I/O TTL ...
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... SDO RC6/TX/ RC6 TX CK RC7/RX/ RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2001 Microchip Technology Inc. Pin Buffer PIC18C801 Type Type TQFP PLCC Description PORTC is a bi-directional I/O port I — I CMOS 43 56 I/O ...
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... RD7 AD7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39541A-page 16 Pin Buffer PIC18C801 Type Type TQFP PLCC Description PORTD is a bi-directional I/O port. These pins have TTL input buffers when external memory is enabled I/O ST I/O ...
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... RE6 AD14 RE7/AD15 59 4 RE7 AD15 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2001 Microchip Technology Inc. Pin Buffer PIC18C801 Type Type TQFP PLCC Description PORTE is a bi-directional I/O port I/O ST I/O TTL 3 14 I/O ST ...
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... CS2 RF5/CS1 13 23 RF5 CS1 RF6/ RF6 LB RF7/ RF7 UB Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39541A-page 18 Pin Buffer PIC18C801 Type Type TQFP PLCC Description PORTF is a bi-directional I/O port I Analog Analog Analog 17 ...
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... RH6/AN10 RH6 AN10 RH7/AN11 — — RH7 AN11 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power 2001 Microchip Technology Inc. Pin Buffer PIC18C801 Type Type TQFP PLCC Description PORTG is a bi-directional I/O port I TTL TTL ...
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... DD 38 VSS VDD Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power DS39541A-page 20 Pin Buffer PIC18C801 Type Type TQFP PLCC Description PORTJ is a bi-directional I/O port I/O ST I/O TTL 40 53 I/O ST I/O TTL 41 54 I/O ...
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... OSC1 pin, as shown in Figure 2-3 and Figure 2-4. PIC18C601/801 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturer’s specifications. 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 2-1: (1) C1 OSC1 XTAL ...
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... PPM ± 20 PPM C EXT ± 50 PPM V SS ± 50 PPM F ± 30 PPM or I/O ± 30 PPM Recommended values: Advance Information ) values and the operat- EXT RC OSCILLATOR MODE Internal OSC1 Clock PIC18C601/801 OSC2/CLKO /4 OSC 100 k EXT C > 20pF EXT 2001 Microchip Technology Inc. ...
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... Comparator F IN Crystal Osc OSCIN 2001 Microchip Technology Inc. 2.5 HS4 (PLL) A Phase Lock Loop (PLL) circuit is provided as a soft- ware programmable option for users that want to multi- ply the frequency of the incoming crystal oscillator signal by 4. For an input clock frequency of 6 MHz, the internal clock frequency will be multiplied to 24 MHz ...
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... PIC18C601/801 T /4 OSC 4 x PLL SLEEP T OSC T1OSCEN Enable Oscillator Clock Source option for other modules and Advance Information T SCLK Clock Source 2001 Microchip Technology Inc. ...
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... After the SCS0 bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchroniza- tion cycles are counted from the Timer1 oscillator, oper- ation resumes. No additional delays are required after the synchronization cycles. 2001 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 — ...
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... Note: Delay on internal system clock is eight oscillator cycles for synchronization. FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, LP T1OSI OSC1 OSC2 Internal System Clock SCS0 (OSCCON<0>) Program Counter PC Note 1024T (drawing not to scale). OST OSC DS39541A-page SCS OST T OSC Advance Information SCS 2001 Microchip Technology Inc. ...
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... Counter Note 1024T (drawing not to scale). OST OSC 2001 Microchip Technology Inc. put is not used, so the system oscillator will come from OSC1 directly and additional delay will required. A timing diagram indicating the transition from PLL the Timer1 oscillator to the main oscillator for HS4 mode is shown in Figure 2-9 ...
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... PLL to lock at high frequen- cies. The PWRT timer is used to provide an additional time-out, called T ample time to lock to the incoming clock frequency. At logic low At logic low Advance Information (parameter PWRT (parameter #7), to allow the PLL PLL OSC2 Pin 2001 Microchip Technology Inc. ...
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... RC OSC Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations. 2001 Microchip Technology Inc. PIC18C601/801 Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal oper- ation. Status bits from the RCON register, RI, TO, PD and POR, are set or cleared differently in different RESET situations, as indicated in Table 3-2 ...
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... This is useful for testing purposes or to synchronize more than one PIC18C601/801 device operating in parallel. Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all registers. to rise Advance Information 2001 Microchip Technology Inc. ...
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... Interrupt wake-up from SLEEP Legend unchanged unknown unimplemented bit, read as '0 reserved, maintain ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (000008h or 000018h). 2001 Microchip Technology Inc. (2) Power-up PWRTEN = 1 ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39541A-page 32 T PWRT T OST T PWRT T PWRT Advance Information ) DD ): CASE OST ): CASE OST 2001 Microchip Technology Inc. ...
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... FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET T = 1024 clock cycles. OST max. First three stages of the PWRT timer. PLL 2001 Microchip Technology Inc. PIC18C601/801 ) DEADTIME T PWRT T OST T PWRT T ...
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... Microchip Technology Inc. ...
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... See Table 3-2 for RESET value for specific condition. 5: This is not a physical register indirect pointer that addresses another register. The contents returned is the value contained in the addressed register. 2001 Microchip Technology Inc. MCLR Reset WDT Reset Reset Instruction Stack Over/Underflow Reset ...
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... Microchip Technology Inc. ...
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... See Table 3-2 for RESET value for specific condition. 5: This is not a physical register indirect pointer that addresses another register. The contents returned is the value contained in the addressed register. 2001 Microchip Technology Inc. MCLR Reset WDT Reset Reset Instruction Stack Over/Underflow Reset ...
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... PIC18C601/801 NOTES: DS39541A-page 38 Advance Information 2001 Microchip Technology Inc. ...
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... If execution takes place from outside of “Boot RAM”, the external system bus and all of its con- trol signals are activated again. Figure 4-3 and Figure 4-4 show the program memory map and stack for PIC18C601 and PIC18C801, when the PGRM bit is set. Advance Information DS39541A-page 39 ...
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... DS39541A-page 40 FIGURE 4-2: PC<20:0> Stack Level 1 Stack Level 31 RESET Vector High Priority Interrupt Vector Low Priority Interrupt Vector External Program Memory Advance Information PROGRAM MEMORY MAP AND STACK FOR PIC18C801 (PGRM = 0) 21 0000h 0008h 0018h 1FFFFFh 2001 Microchip Technology Inc. ...
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... FIGURE 4-3: PROGRAM MEMORY MAP AND STACK FOR PIC18C601 (PGRM = 1) On-Chip Boot RAM INTERNAL MEMORY 2001 Microchip Technology Inc. PIC18C601/801 PC<20:0> 21 Stack Level 1 Stack Level 31 RESET Vector High Priority Interrupt Vector Low Priority Interrupt Vector External Program Memory Read ’0’ ...
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... PIC18C601/801 FIGURE 4-4: PROGRAM MEMORY MAP AND STACK FOR PIC18C801 (PGRM = 1) On-Chip Boot RAM INTERNAL MEMORY DS39541A-page 42 PC<20:0> 21 Stack Level 1 Stack Level 31 RESET Vector High Priority Interrupt Vector Low Priority Interrupt Vector External Program Memory 1FFE00h External Table Memory 1FFFFFh EXTERNAL MEMORY ...
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... SFR registers. Status bits STKOVF and STKUNF in STKPTR register, indicate whether stack over/underflow has occurred or not. 2001 Microchip Technology Inc. PIC18C601/801 4.2.1 TOP-OF-STACK ACCESS The top of the stack is readable and writable. Three ...
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... Bit is set ’0’ = Bit is cleared Return Address Stack 11111 11110 11101 TOSL 34h 00011 001A34h Top-of-Stack 00010 000D58h 00001 (1) 000000h 00000 Advance Information R/W-0 R/W-0 R/W-0 SP2 SP1 SP0 bit Clearable bit STKPTR<4:0> 00010 2001 Microchip Technology Inc. ...
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... STKFUL or STKUNF bit and then cause a RESET. The STKFUL or STKUNF bits are only cleared by the user software or a POR. 2001 Microchip Technology Inc. PIC18C601/801 4.3 Fast Register Stack A “fast return” option is available for interrupts and calls. ...
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... Q1 through Q4. The clocks and instruction execu- tion flow are shown in Figure 4- PC+2 Fetch INST (PC+2) Execute INST (PC) Advance Information Internal Phase Clock PC+4 Fetch INST (PC+4) Execute INST (PC+2) 2001 Microchip Technology Inc. ...
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... INSTRUCTIONS IN PROGRAM MEMORY Instruction — MOVLW 055h GOTO 000006h MOVFF 123h, 456h — 2001 Microchip Technology Inc. PIC18C601/801 4.7 Instructions in Program Memory The program memory is addressed in bytes. Instruc- tions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = ’ ...
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... CASE 1: Source Code REG1 ; is RAM location 0? REG1, REG2 ; No, execute 2-word instruction ; 2nd operand holds address of REG2 REG3 ; continue code CASE 2: Source Code REG1 ; is RAM location 0? REG1, REG2 ; Yes ; 2nd operand executed as NOP REG3 ; continue code Advance Information 2001 Microchip Technology Inc. ...
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... GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access bank. Section 4.10 pro- vides a detailed description of the Access bank. 2001 Microchip Technology Inc. PIC18C601/801 4.9.1 GENERAL PURPOSE REGISTER FILE The register file can be accessed either directly or indi- rectly ...
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... Note: Successive attempts to unlock the Combi- nation Lock must be separated by at least three instruction cycles. Advance Information U-0 W-0 W-0 — CMLK1 CMLK0 bit Bit is unknown 2001 Microchip Technology Inc. ...
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... UNLOCK_N_MODIFY @REG MACRO BCF INTCON, GIE BSF PSPCON, CMLK1 BSF PSPCON, CMLK0 MOVWF @REG BSF INTCON, GIE ENDM MOVLW 5Ah UNLOCK_N_MODIFY OSCCON FIGURE 4-7: THE DATA MEMORY MAP FOR PIC18C801/601 (PGRM = 0) BSR<3:0> 00h = 0000b Bank 0 FFh 00h = 0001b Bank 1 FFh 00h ...
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... BSR is ignored and this Access RAM bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The next 128 bytes are Special Function Registers (from Bank 15). When the BSR is used to specify the RAM location that the instruction uses. 2001 Microchip Technology Inc. ...
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... FE5h POSTDEC1 FC5h FE4h PREINC1 FC4h FE3h PLUSW1 FC3h FE2h FSR1H FC2h FE1h FSR1L FC1h FE0h BSR FC0h 2001 Microchip Technology Inc. PIC18C601/801 INDF2 FBFh CCPR1H POSTINC2 FBEh CCPR1L POSTDEC2 FBDh CCP1CON F9Dh PREINC2 FBCh CCPR2H PLUSW2 FBBh CCPR2L FSR2H FBAh ...
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... Legend x = unknown unchanged unimplemented value depends on condition reserved Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2: These registers can only be modified when the Combination Lock is open. 3: These registers are available on PIC18C801 only. DS39541A-page 54 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2: These registers can only be modified when the Combination Lock is open. 3: These registers are available on PIC18C801 only. 2001 Microchip Technology Inc. Bit 5 ...
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... Legend x = unknown unchanged unimplemented value depends on condition reserved Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2: These registers can only be modified when the Combination Lock is open. 3: These registers are available on PIC18C801 only. DS39541A-page 56 Bit 5 Bit 4 Bit 3 Bit 2 — ...
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... Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset. 2: These registers can only be modified when the Combination Lock is open. 3: These registers are available on PIC18C801 only. 2001 Microchip Technology Inc. Bit 5 ...
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... Section 4.12 provides a description of indirect address- ing, which allows linear addressing of the entire RAM space. (3) from opcode 0 (3) 00h 01h 000h 100h Data (1) Memory 0FFh 1FFh Bank 0 Bank 1 Advance Information 0Eh 0Fh E00h F00h EFFh FFFh Bank 14 Bank 15 2001 Microchip Technology Inc. ...
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... A read from INDF1 reads the data from the address indicated by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2001 Microchip Technology Inc. If INDF0, INDF1, or INDF2 are read indirectly via an FSR, all ’0’s are read (zero bit is set). Similarly, if INDF0, INDF1, or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the STATUS bits are not affected ...
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... PIC18C601/801 FIGURE 4-11: INDIRECT ADDRESSING 11 FSRnH Location Select Note 1: For register file map detail, see Table 4-2. DS39541A-page 60 Indirect Addressing FSR Register FSRnL 0000h Data (1) Memory 0FFFh Advance Information 2001 Microchip Technology Inc. ...
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... Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. For example, CLRF STATUS will clear all implemented bits and set the Z bit. This leaves the STATUS register as ---0 0100 (where - = unimplemented). ...
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... Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. U-0 U-0 R/W-1 R/W-1 r — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R/W-1 R/W-0 U-0 PD POR r bit Bit is unknown 2001 Microchip Technology Inc. ...
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... FLASH, EPROM, SRAM, etc. Memory mapped peripherals may also be accessed. The External Memory Interface physical implementa- tion includes pins on the PIC18C601 and pins on the PIC18C801. These pins are reserved for external address/data bus functions. REGISTER 5-1: MEMCON REGISTER R/W-0 ...
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... D<7:0> A<17:0> 373 Function Address Latch Enable (ALE) control pin Output Enable (OE) control pin Write Low (WRL) control pin Byte address bit 0 Chip Select I/O (See Section 5.4) Chip Select 1 (See Section 5.4) Advance Information A<x:1> A0 D<7:0> ( 2001 Microchip Technology Inc. ...
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... OE 5.2.2 8-BIT DE-MULTIPLEXED MODE The 8-bit De-Multiplexed mode applies only to the PIC18C801. Data and address lines are available sep- arately. External components are not necessary in this mode. For 8-bit De-Multiplexed mode on the PIC18C801, the instructions are fetched as two 8-bit bytes on a dedi- cated data bus (PORTJ) ...
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... PIC18C601/801 FIGURE 5-3: 8-BIT DE-MULTIPLEXED MODE EXAMPLE BA0 A<19:16>, AD<15:0> D<7:0> PIC18C801 ALE CS1 OE WRL Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. TABLE 5-2: 8-BIT DE-MULTIPLEXED MODE CONTROL SIGNALS Name 8-bit De-Mux Mode RG0/ALE ...
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... Byte Write • 16-bit Word Write • 16-bit Byte Select These three different configurations allow the designer maximum flexibility in using 8-bit and 16-bit memory devices. FIGURE 5-5: 16-BIT BYTE WRITE MODE EXAMPLE PIC18C801 AD<15:8> AD<7:0> ALE A<19:16> CS1 OE WRH WRL Note 1: This signal only applies to Table Writes ...
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... WRH Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes. 5.3.3 16-BIT BYTE SELECT MODE Figure 5-7 shows an example of 16-bit Byte Select mode for the PIC18C801. FIGURE 5-7: 16-BIT BYTE SELECT MODE EXAMPLE PIC18C801 AD<7:0> AD<15:8> ...
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... Q1 A16, AD<15:8> AD<7:0> BA0 ALE OE WRH ‘1’ ‘1’ WRL 2001 Microchip Technology Inc. 18C801 16-bit Mode ALE Address Latch Enable (ALE) control pin OE Output Enable (OE) control pin WRL Write Low (WRL) control pin WRH Write High (WRH) control pin ...
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... Chip select signals are used to select regions of exter- nal memory and I/O devices for access. The PIC18C801 has three chip selects and all are program- mable. The chip select signals are CS1, CS2 and CSIO. CS1 and CS2 are general purpose chip selects that are used to enable large portions of program mem- ory ...
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... PROGRAM MEMORY 000000h 1FFDFFh 1FFE00h 1FFFFFh = CS1 ACTIVE 2001 Microchip Technology Inc. PIC18C601/801 A 00h value in the CSEL2 register will disable the CS2 signal and will configure the RF4 pin as I/O. Figure 5-9 shows an example address map for CS2. 5.4.3 CHIP SELECT I/O (CSIO) ...
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... See Section 6.0 for more details. Since the device execution is tied to instruction fetches, there is no need to execute faster than the fetch rate. So, if the program needs to be slowed, the processor speed must be slowed with a different T DS39541A-page 72 time. CY Advance Information 2001 Microchip Technology Inc. ...
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... TBLPTRU TBLPTRH Instruction: TBLWT * Note 1: Table Pointer points to a byte in external program memory. 2001 Microchip Technology Inc. PIC18C601/801 Table Read operations retrieve data from external pro- gram memory and place it into the data memory space. Figure 6-1 shows the operation of a Table Read with program and data memory ...
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... TBLWRT instructions. These instructions can update the TBLPTR in one of four ways, based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low order 21-bits. Operation on Table Pointer Advance Information byte). These three registers 2001 Microchip Technology Inc. ...
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... TBLRD* from 007554h Instruction INST(PC-2) Execution 2001 Microchip Technology Inc. PIC18C601/801 Table Reads from external program memory are performed one byte at a time. If the external interface is 8-bit, the bus interface circuitry in TABLAT will load the external value into TABLAT. If the external interface is ...
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... MOVLW 55h from 199E67h from 007556h TBLRD Cycle1 TBLRD Cycle2 Advance Information 03AACh 55h ’1’ ’1’ Opcode Fetch ADDLW 55h from 007558h MOVLW 0F55h 3AACh ’1’ ’1’ Opcode Fetch ADDLW 55h from 007558h MOVLW 2001 Microchip Technology Inc. ...
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... Write a byte to location 0020h CLRF TBLPTRU ; clear upper 5 bits of TBLPTR CLRF TBLPTRH ; clear higher 8 bits of TBLPTR MOVLW 20h ; Load 20h into MOVWF TBLPTRL ; TBLPTRL MOVLW 55h ; Load 55h into MOVWF TBLAT ; TBLAT TBLWT* ; Write it 2001 Microchip Technology Inc. PIC18C601/801 Advance Information DS39541A-page 77 ...
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... Instruction INST(PC-2) Execution DS39541A-page 03Ah CCFh ABh 55h 0Eh 92h 33h Opcode Fetch TBLWT 92h MOVLW 55h to 199E67h from 007556h TBLWT Cycle1 TBLWT Cycle2 Advance Information 03Ah ACh 55h 0Fh Opcode Fetch ADDLW 55h from 007558h MOVLW 2001 Microchip Technology Inc. ...
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... A<19:8> 03Ah 08h 00h AD<7:0> BA0 ALE OE ’1’ WRH WRL Memory Opcode Fetch Cycle TBLWT* from 007554h Instruction INST(PC-2) Execution 2001 Microchip Technology Inc. PIC18C601/801 03Ah CCFh 55h 0Eh 92h Opcode Fetch TBLWT 92h MOVLW 55h to 199E67h from 007556h TBLWT Cycle1 ...
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... Execution DS39541A-page 3AACh 6FF4h 000Ch CF33h 5656h TBLWT 56h Opcode Fetch to 199E66h TBLWT* from 007558h TBLWT*+ Cycle2 MOVWF Advance Information CF33h 9292h 3AADh 0E55h Opcode Fetch TBLWT 92h to 199E67h MOVLW 55h from 00755Ah TBLWT* Cycle1 TBLWT* Cycle2 2001 Microchip Technology Inc. ...
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... Instruction INST(PC-2) TBLWT*+ Cycle1 TBLWT*+ Cycle2 Execution 2001 Microchip Technology Inc. During a TBLWT cycle to an odd address, where TBLPTR<0> the TABLAT data is presented on the upper byte of the AD<15:0> bus. The contents of the holding latch are presented on the lower byte of the AD< ...
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... Figure 6-10 shows the timing associated with this mode 6FF4h 3AACh 000Ch CF33h 5656h TBLWT 56h Opcode Fetch to 199E66h TBLWT* from 007558h MOVWF Advance Information CF33h 9292h 3AADh 0E55h Opcode Fetch TBLWT 92h MOVLW 55h to 199E67h from 00755Ah TBLWT* Cycle1 TBLWT* Cycle2 2001 Microchip Technology Inc. ...
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... BA0 ALE OE Opcode Fetch MOVLW 55h from 007556h 2001 Microchip Technology Inc. The WAIT<1:0> bits in the MEMCON register will select extra T The wait will occur on Q4. The default setting of the wait on power- assert a maximum wait of 3T memories will work in Microprocessor mode immedi- ately after RESET ...
Page 84
... Q2 Q3 Apparent Q Actual A<19:16> 0h 3AABh AD<15:0> BA0 ALE OE WRH ’1’ WRL ’1’ Opcode Fetch MOVLW 55h from 007556h DS39541A-page 0Ch 0E55h CF33h Table Read of 92h from 199E67h Advance Information 9256h ’1’ ’1’ 1T Wait CY 2001 Microchip Technology Inc. ...
Page 85
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply 2001 Microchip Technology Inc. PIC18C601/801 The performance increase allows the device to be used in some applications previously reserved for Digital Signal Processors. Table 7-1 shows a performance comparison between enhanced devices using the single cycle hardware mul- tiply, and performing the same function without the hardware multiply ...
Page 86
... PRODH:PRODL PRODL RES1 ; Add cross PRODH products RES2 ; WREG ; RES3 ; ARG1H, WREG ; ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 ; Add cross PRODH products RES2 ; WREG ; RES3 ; SIGNED MULTIPLICATION ALGORITHM ARG2H:ARG2L 16 ARG2H ARG2L ARG2H ARG2L ARG2H<7> ARG1H:ARG1L ARG1H<7> ARG2H:ARG2L 2 ) 2001 Microchip Technology Inc. ...
Page 87
... ARG1 MOVFF ARG1L, WREG ; SUBWF RES2 ; MOVFF ARG1H, WREG ; SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H ARG1H:ARG1L neg? GOTO CONT_CODE ; no, done MOVFF ARG2L, WREG ; SUBWF RES2 ; MOVFF ARG2H, WREG ; SUBWFB RES3 ; CONT_CODE : 2001 Microchip Technology Inc. products products Advance Information PIC18C601/801 DS39541A-page 87 ...
Page 88
... PIC18C601/801 NOTES: DS39541A-page 88 Advance Information 2001 Microchip Technology Inc. ...
Page 89
... Individual interrupts can be disabled through their cor- responding enable bits. 2001 Microchip Technology Inc. PIC18C601/801 When the IPEN bit is cleared (default state), the inter- rupt priority feature is disabled and interrupts are ...
Page 90
... INT2E INT2P IPEN IPEN GIEL/PEIE IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0F INT0E INT1F INT1E INT1P INT2F INT2E INT2P Advance Information Wake- SLEEP mode Interrupt to CPU Vector to location 0008h GIEH/GIE Interrupt to CPU Vector to Location 0018h GIEL\PEIE 2001 Microchip Technology Inc. ...
Page 91
... Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2001 Microchip Technology Inc. PIC18C601/801 8.1.1 INTCON REGISTERS ...
Page 92
... This feature allows software polling. DS39541A-page 92 R/W-1 R/W-1 U-0 INTEDG1 INTEDG2 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R/W-1 U-0 R/W-1 TMR0IP — RBIP bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 93
... Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2001 Microchip Technology Inc. PIC18C601/801 U-0 R/W-0 R/W-0 — ...
Page 94
... The Reset Control (RCON) register contains the bit that is used to enable prioritized interrupts (IPEN). U-0 U-0 R/W-1 R/W-1 r — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R/W-1 R/W-0 U-0 PD POR r bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 95
... No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. R/W-0 R-0 R-0 R/W-0 ADIF RCIF TXIF SSPIF W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 96
... Value at POR DS39541A-page 96 U-0 U-0 U-0 R/W-0 — — — BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R/W-0 R/W-0 R/W-0 LVDIF TMR3IF CCP2IF bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 97
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 R/W-0 R/W-0 R/W-0 RCIE TXIE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 98
... Value at POR DS39541A-page 98 U-0 U-0 U-0 R/W-0 — — — BCLIE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R/W-0 R/W-0 R/W-0 LVDIE TMR3IE CCP2IE bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 99
... TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 R/W-1 R/W-1 R/W-1 RCIP TXIP SSPIP W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 100
... Value at POR DS39541A-page 100 U-0 U-0 U-0 R/W-1 — — — BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R/W-1 R/W-1 R/W-1 LVDIP TMR3IP CCP2IP bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 101
... BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2001 Microchip Technology Inc. PIC18C601/801 in the TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clear- ing enable bit TMR0IE (INTCON register). Interrupt prior- ity for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2 register) ...
Page 102
... PIC18C601/801 NOTES: DS39541A-page 102 Advance Information 2001 Microchip Technology Inc. ...
Page 103
... The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. Note Power-on Reset, PORTA pins RA3:RA0 and RA5 default to analog inputs. 2001 Microchip Technology Inc. PIC18C601/801 EXAMPLE 9-1: CLRF PORTA CLRF ...
Page 104
... Bit 4 Bit 3 Bit 2 Bit 1 RA4 RA3 RA2 RA1 PCFG2 PCFG1 Advance Information - REF + REF Value on Value on all Bit 0 POR, other BOR RESETS RA0 --0x 0000 --uu uuuu -xxx xxxx -uuu uuuu -111 1111 -111 1111 PCFG0 --00 0000 --uu uuuu 2001 Microchip Technology Inc. ...
Page 105
... enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). 2001 Microchip Technology Inc. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is per- formed by clearing bit RBPU (INTCON2 register). The weak pull-up is automatically turned off when the port pin is configured as an output ...
Page 106
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). DS39541A-page 106 V DD Weak P Pull-up (1) I/O pin TTL Input Buffer D RD Port and Data Latch TRIS Latch TRISB RD LATB PORTB Schmitt Trigger Buffer and Advance Information V DD Weak P Pull- (1) I/O pin TTL Input Buffer 2001 Microchip Technology Inc. ...
Page 107
... INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend unknown unchanged. Shaded cells are not used by PORTD. 2001 Microchip Technology Inc. Function Input/output pin or external interrupt 0 input. Internal software programmable weak pull-up. Input/output pin or external interrupt 1 input. Internal software programmable weak pull-up. ...
Page 108
... TRIS OVERRIDE Override Peripheral Yes Timer1 OSC for Timer1/Timer3 Yes Timer1 OSC for Timer1/Timer3 No — Yes 2 SPI/I C Master Clock Yes Data Out Yes SPI Data Out Yes USART Async Xmit, Sync Clock Yes USART Sync Data Out 2001 Microchip Technology Inc. ...
Page 109
... RC5 LATC LATC Data Output Register TRISC PORTC Data Direction Register Legend unknown unchanged 2001 Microchip Technology Inc. PIC18C601/801 Function Input/output port pin or Timer1 oscillator output or Timer1/Timer3 clock input. Input/output port pin, Timer1 oscillator input. Input/output port pin or Capture1 input/Compare1 output/ PWM1 output ...
Page 110
... FIGURE 9-7: Data Bus D WR LATD PORTD Data Latch D WR TRISD CK TRIS Latch RD PORTD Note: I/O pins have diode protection to V Advance Information PORTD BLOCK DIAGRAM IN I/O MODE RD LATD Q I/O pin Q Schmitt Trigger Input Buffer RD TRISD and 2001 Microchip Technology Inc. ...
Page 111
... PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTD Data Bus WR LATD or PORTD WR TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Note 1: I/O pins have protection diodes to V 2001 Microchip Technology Inc. PIC18C601/801 LATD Port Data 1 CK Data Latch ...
Page 112
... Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode. 2: RDx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an address only for PIC18C801 in 8-bit mode. ...
Page 113
... TRIS Latch RD TRISE Peripheral Enable RD PORTE Peripheral Data In Note 1: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 byte of the address/data bus (AD15:AD8 the high order address byte (A15:A8), if address and data buses are de-multiplexed. Note: On Power-on Reset, PORTE defaults to the system bus ...
Page 114
... System Bus Data/Address Out Control Drive System To Instruction Register Note 1: I/O pins have diode protection to V DS39541A-page 114 LATD Port Data 1 CK Data Latch TRIS Latch TRISE Instruction Read and Advance Information (1) I/O pin TTL Input Buffer 2001 Microchip Technology Inc. ...
Page 115
... Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus mode. 2: REx is used as a multiplexed address/data bus for PIC18C601 and PIC18C801 in 16-bit mode, and as an address only for PIC18C801 in 8-bit mode. ...
Page 116
... PORTF pins, RF3 and RF5, are multiplexed with two of the integrated chip select signals CSIO and CS1. For PIC18C801, pin RF4 is multiplexed with chip select sig- nal CS2, while for PIC18C601 multiplexed with system bus signal A16. For PIC18C801 devices, both ...
Page 117
... Note 1: I/O pins have diode protection to V FIGURE 9-13: RF7:RF6 PINS BLOCK DIAGRAM RD PORTF Data Bus WR LATF or PORTF WR TRISF UB/LB Out System Bus WM = ’01’ Control Drive System Note 1: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 LATF Port Data 1 CK Data Latch ...
Page 118
... ST RF5/CS1 bit5 ST RF6/LB bit6 ST RF7/UB bit7 ST Legend Schmitt Trigger input Note 1: CS2 is available only on PIC18C801. TABLE 9-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Name Bit 7 Bit 6 Bit 5 TRISF PORTF Data Direction Control Register PORTF Read PORTF pin/Write PORTF Data Latch LATF ...
Page 119
... LATG ; Alternate method ; to clear output ; data latches MOVLW 04h ; Value used to ; initialize data ; direction MOVWF TRISG ; Set RG1:RG0 as outputs ; RG2 as input ; RG4:RG3 as outputs 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 9-14: RD LATG Data Bus D WR LATG CK or PORTG Data Latch D WR TRISG ...
Page 120
... Input/output port pin or Byte Address 0 signal for external memory Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WAIT0 — — WM1 WM0 Advance Information (1) I/O pin Value on: Value on all POR, other BOR RESETS ---1 1111 ---1 1111 ---x xxxx ---u uuuu ---x xxxx ---u uuuu 0000 --00 0000 --00 2001 Microchip Technology Inc. ...
Page 121
... PORTH, LATH, and TRISH Registers Note: PORTH is available only on PIC18C801 devices. PORTH is an 8-bit wide, bi-directional I/O port. The cor- responding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode) ...
Page 122
... System Bus Address Out Control Drive System To Instruction Register Note 1: I/O pins have diode protection to V DS39541A-page 122 LATD Port Data 1 CK Data Latch TRIS Latch RD TRISH Instruction Read and Advance Information (1) I/O pin TTL Input Buffer 2001 Microchip Technology Inc. ...
Page 123
... ST (1) RH6/AN10 bit6 ST (1) RH7/AN11 bit7 ST Legend Schmitt Trigger input Note 1: PORTH is available only on PIC18C801 devices. TABLE 9-16: SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Name Bit 7 Bit 6 Bit 5 TRISH PORTH Data Direction Control Register PORTH Read PORTH pin/Write PORTH Data Latch ...
Page 124
... PIC18C601/801 9.9 PORTJ, LATJ, and TRISJ Registers Note: PORTJ is available only on PIC18C801 devices. PORTJ is an 8-bit wide, bi-directional I/O port. The cor- responding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode) ...
Page 125
... PORTJ BLOCK DIAGRAM IN SYSTEM DATA BUS MODE RD PORTJ Data Bus WR LATJ or PORTJ WR TRISJ External Enable System Bus Data Out Control Drive System To Instruction Register Note 1: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 LATD Port Data 1 CK Data Latch ...
Page 126
... ST/TTL (1) RJ6/D6 bit6 ST/TTL (1) RJ7/D7 bit7 ST/TTL Legend Schmitt Trigger input, TTL = TTL input Note 1: PORTJ is available only on PIC18C801 devices. TABLE 9-18: SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Name Bit 7 Bit 6 Bit 5 TRISJ PORTJ Data Direction Control Register PORTJ Read PORTJ pin/Write PORTJ Data Latch ...
Page 127
... Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. Register 10-1 shows the Timer0 Control register (T0CON). Figure 10-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 10-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
Page 128
... Sync with Internal TMR0L Clocks delay PSA and Advance Information Data Bus 8 TMR0L delay) Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> 2001 Microchip Technology Inc. ...
Page 129
... T08BIT TRISA — PORTA Data Direction Register Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 2001 Microchip Technology Inc. 10.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol (i.e., it can be changed “on-the-fly” during program execution) ...
Page 130
... Note: Timer1 is disabled on POR. R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 131
... T13CKI/T1OSO T1OSI Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. 2001 Microchip Technology Inc. When TMR1CS is clear, Timer1 increments every instruction cycle. When TMR1CS is set, Timer1 incre- ments on every rising edge of the external clock input or the Timer1 oscillator, if enabled ...
Page 132
... Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. DS39541A-page 132 8 Special Event Trigger 0 TMR1L 1 TMR1ON T1SYNC On/Off 1 Prescaler OSC Internal 0 (1) Clock TMR1CS T1CKPS1:T1CKPS0 Advance Information Synchronized Clock Input Synchronize det 2 SLEEP Input 2001 Microchip Technology Inc. ...
Page 133
... TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR regis- ters). This interrupt can be enabled/disabled by setting/ clearing TMR1 interrupt enable bit TMR1IE (PIE registers). 2001 Microchip Technology Inc. PIC18C601/801 11.4 Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in Compare mode ...
Page 134
... POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF -000 0000 -000 0000 TMR1IE -000 0000 -000 0000 TMR1IP -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0-00 0000 u-uu uuuu 2001 Microchip Technology Inc. ...
Page 135
... Prescaler Prescaler Prescaler is 16 Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 12.1 Timer2 Operation Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is read- able and writable, and is cleared on any device RESET. ...
Page 136
... TMR2IF (1) Value on Value on Bit 0 all other POR, BOR RESETS RBIF 0000 000x 0000 000u TMR1IF -000 0000 -000 0000 TMR1IE -000 0000 -000 0000 TMR1IP -000 0000 -000 0000 0000 0000 0000 0000 1111 1111 1111 1111 2001 Microchip Technology Inc. ...
Page 137
... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 Figure 13 simplified block diagram of the Timer3 module. Register 13-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 138
... Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Trigger T3CCPx TMR3 CLR TMR3L TMR3ON On/Off OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Advance Information Synchronized Clock Input Synchronize det 2 SLEEP Input Synchronized 0 Clock Input 1 T3SYNC Synchronize Prescaler det 2 SLEEP Input 2001 Microchip Technology Inc. ...
Page 139
... T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer3 module. 2001 Microchip Technology Inc. 13.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3 ...
Page 140
... PIC18C601/801 NOTES: DS39541A-page 140 Advance Information 2001 Microchip Technology Inc. ...
Page 141
... Trigger special event (CCPIF bit is set, reset TMR1 or TMR3) 11xx = PWM mode Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger. Therefore, operation of a CCP module in the following sections is described, with respect to CCP1. ...
Page 142
... The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Syn- chronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer used with each CCP module is selected in the T3CON register. Interaction Advance Information 2001 Microchip Technology Inc. ...
Page 143
... CCP2M3:CCP2M0 Q’s Note: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 14-1 shows the recom- mended method for switching between capture pres- calers ...
Page 144
... Set Flag bit CCP1IF Output Logic Match CCP1M3:CCP1M0 T3CCP2 Mode Select TMR1H Set Flag bit CCP2IF T3CCP1 T3CCP2 Output Logic Match CCP2M3:CCP2M0 Mode Select and Advance Information CCPR1H CCPR1L Comparator 1 0 TMR1L TMR3H TMR3L 0 1 Comparator CCPR2H CCPR2L 2001 Microchip Technology Inc. ...
Page 145
... TMR3H Holding register for the Most Significant Byte of the 16-bit TMR3 register T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. 2001 Microchip Technology Inc. PIC18C601/801 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE ...
Page 146
... If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. Advance Information [(PR2 • 4 • T • OSC (TMR2 prescale value) (CCPR1L:CCP1CON<5:4>) • T • (TMR2 prescale value) OSC F OSC --------------- log F PWM = -----------------------------bits log 2 2001 Microchip Technology Inc. ...
Page 147
... IPR2 — — — Legend unknown unchanged, — = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. 2001 Microchip Technology Inc. PIC18C601/801 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON ...
Page 148
... PIC18C601/801 NOTES: DS39541A-page 148 Advance Information 2001 Microchip Technology Inc. ...
Page 149
... Serial Peripheral Interface (SPI) 2 • Inter-Integrated Circuit Full Master mode - Slave mode (with general address call) 2 The I C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode 2001 Microchip Technology Inc. PIC18C601/801 Advance Information DS39541A-page 149 ...
Page 150
... MSSP Control Register 2 (SSPCON2). R-0 R-0 R-0 CKE D mode only mode only mode only modes Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R-0 R-0 R bit Bit is unknown 2001 Microchip Technology Inc. ...
Page 151
... I C Slave mode, 7-bit address with START and STOP bit interrupts enabled 2 1111 = I C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. PIC18C601/801 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 ...
Page 152
... C Master mode only Master mode only Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R/W-0 R/W-0 R/W-0 PEN RSEN SEN bit module is not in the IDLE x = Bit is unknown 2001 Microchip Technology Inc. ...
Page 153
... Clock edge (output data on rising/falling edge of SCK) • Clock rate (Master mode only) • Slave Select mode (Slave mode only) Figure 15-1 shows the block diagram of the MSSP module, when in SPI mode. 2001 Microchip Technology Inc. PIC18C601/801 FIGURE 15-1: Read SDI SDO ...
Page 154
... SCK (Slave mode) must have TRISC<3> bit set • RA5 must be configured as digital I/O using ADCON1 register • SS must have TRISA<5> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Advance Information 2001 Microchip Technology Inc. ...
Page 155
... Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF 2001 Microchip Technology Inc. PIC18C601/801 The clock polarity is selected by appropriately program- ming the CKP bit (SSPCON1 register). This, then, would give waveforms for SPI communication as shown in Figure 15-2, Figure 15-4, and Figure 15-5, where the MSb is transmitted first. In Master mode, the ...
Page 156
... SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function), since it cannot create a bus conflict. bit6 bit7 bit7 Advance Information . DD bit0 bit0 Next Q4 Cycle after Q2 2001 Microchip Technology Inc. ...
Page 157
... CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit7 SDI (SMP = 0) bit7 Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF 2001 Microchip Technology Inc. PIC18C601/801 bit6 bit5 bit4 bit2 bit3 bit6 bit2 bit5 bit4 bit3 Advance Information bit1 bit0 bit0 Next Q4 Cycle after Q2 ...
Page 158
... RESETS RBIF 0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 BF 0000 0000 0000 0000 2001 Microchip Technology Inc. ...
Page 159
... Match Detect SSPADD reg START and STOP bit Detect Note: I/O pins have diode protection 2001 Microchip Technology Inc. The SSPCON1 register allows control of the I ation. The SSPM3:SSPM0 mode selection bits (SSPCON1 register) allow one of the following I modes to be selected: 2 • I ...
Page 160
... START bit. If the SDA line was low (ACK), the trans- mit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Pin RC3/SCK/SCL should be enabled by setting bit CKP. Advance Information 2001 Microchip Technology Inc. ...
Page 161
... SCL S SSPIF BF SSPOV 2 FIGURE 15- SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA SCL Data in Sampled SSPIF BF CKP 2001 Microchip Technology Inc. Receiving Data ACK ACK Cleared in software SSPBUF register is read Bit SSPOV is set because the SSPBUF register is still full. R ...
Page 162
... Acknowledge (Figure 15-9). Address is compared to General Call Address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Advance Information Receiving Data ACK ’0’ ’1’ 2001 Microchip Technology Inc. ...
Page 163
... FIGURE 15-10: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision Note: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 1. Assert a START condition on SDA and SCL. 2. Assert a Repeated START condition on SDA and SCL. 3. Write to the SSPBUF register initiating transmis- sion of data/address ...
Page 164
... If clock arbitration is taking place, for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure 15-12). SSPM3:SSPM0 SSPADD<6:0> Reload Reload Control BRG Down Counter CLKOUT Advance Information ) on the Master mode, the BRG OSC 2001 Microchip Technology Inc. ...
Page 165
... SDA line held low and the START condition is complete. FIGURE 15-13: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL 2001 Microchip Technology Inc. DX-1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h ...
Page 166
... SSPCON2 is disabled until the Repeated START condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of START bit, SCL = 1 hardware clear RSEN bit and set SSPIF BRG BRG BRG 1st Bit Write to SSPBUF occurs here T BRG Sr = Repeated START Advance Information T BRG 2001 Microchip Technology Inc. ...
Page 167
... BF Status Flag In Transmit mode, the BF bit (SSPSTAT register) is set when the CPU writes to SSPBUF, and is cleared when all eight bits are shifted out. 2001 Microchip Technology Inc. PIC18C601/801 15.4.8.2 WCOL Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’ ...
Page 168
... PIC18C601/801 2 FIGURE 15-15 MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39541A-page 168 Advance Information 2001 Microchip Technology Inc. ...
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... FIGURE 15-16 MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) 2001 Microchip Technology Inc. PIC18C601/801 Advance Information DS39541A-page 169 ...
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... SDA sampled high, P bit (SSPSTAT) is set PEN bit (SSPCON2) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to set up STOP condition Advance Information BRG Cleared in software BRG 2001 Microchip Technology Inc. ...
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... BRG overflow occurs, Release SCL, Slave device holds SCL low. to measure high time interval SCL SDA T BRG 2001 Microchip Technology Inc. PIC18C601/801 15.4.13 SLEEP OPERATION While in SLEEP mode, the I addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled) ...
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... S and P bits are cleared. Sample SDA. While SCL is high, SDA line pulled low by another source data doesn’t match what is driven by the master. Bus collision has occurred. SDA released by Master Advance Information 2 C Set bus collision interrupt (BCLIF) 2001 Microchip Technology Inc. ...
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... S bit and SSPIF set because BCLIF SDA = 0, SCL = 1. S SSPIF 2001 Microchip Technology Inc. PIC18C601/801 If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-23). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count ...
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... SDA = 0, SCL = 1 Set S Set SSPIF BRG T BRG S SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 SDA = 0, SCL = 1 Set SSPIF Advance Information Interrupt cleared in software ’0’ ’0’ ’0’ Interrupts cleared in software 2001 Microchip Technology Inc. ...
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... BCLIF Set BCLIF, release SDA and SCL. RSEN S SSPIF 2001 Microchip Technology Inc. PIC18C601/801 reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. ...
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... T T BRG BRG T BRG SCL goes low before SDA goes high, set BCLIF Advance Information SDA sampled T BRG low after T , BRG set BCLIF ’0’ ’0’ T BRG ’0’ ’0’ 2001 Microchip Technology Inc. ...
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... TX9D: 9th bit of Transmit Data. Can be Address/Data bit or a parity bit. Legend Readable bit - n = Value at POR 2001 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) The SPEN (RCSTA register) and the TRISC< ...
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... Value at POR DS39541A-page 178 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADDEN W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Advance Information R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown 2001 Microchip Technology Inc. ...
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... SPEN RX9 SREN SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used by the BRG. 2001 Microchip Technology Inc. Example 16-1 shows the calculation of the baud rate error for the following conditions MHz OSC Desired Baud Rate = 9600 ...
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... SPBRG SPBRG % value value KBAUD ERROR (decimal) (decimal 185 9.60 0 131 92 19. 74.54 -2. 97.48 +1. 1267. 255 4.95 - 255 32.768 kHz SPBRG SPBRG % value value KBAUD ERROR (decimal) (decimal) 0.30 +1.14 207 1.17 -2.48 6 103 8. 255 0.03 - 255 2001 Microchip Technology Inc. ...
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... 9.32 19 18.64 76 300 500 HIGH 62. 55.93 LOW 0.24 - 255 0.22 2001 Microchip Technology Inc. 20 MHz SPBRG % value ERROR (decimal +0.16 129 -1.36 32 +1.73 15 +1. +4. 255 10 MHz 7.15909 MHz SPBRG % % value ERROR KBAUD ERROR (decimal ...
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... Advance Information 5.0688 MHz SPBRG SPBRG % value value KBAUD ERROR (decimal) (decimal 185 2.40 0 131 46 9. 18.64 -2. 79.20 +3. 316. 255 1.24 - 255 32.768 kHz SPBRG SPBRG % value value KBAUD ERROR (decimal) (decimal) 207 0.29 -2. 2. 255 0.008 - 255 2001 Microchip Technology Inc. ...
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... SPBRG Baud Rate Generator Note: I/O pins have diode protection 2001 Microchip Technology Inc. Once the TXREG register transfers the data to the TSR register (occurs in one T empty and flag bit TXIF (PIR registers) is set. This inter- rupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and can- not be cleared in software ...
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... BOR RESETS RBIF 0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...
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... Baud Rate Generator RC7/RX/DT Pin Buffer and Control SPEN Note: I/O pins have diode protection to V 2001 Microchip Technology Inc. PIC18C601/801 16.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. Steps to follow when setting up an Asynchronous Reception with Address Detect Enable: 1 ...
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... BOR RESETS RBIF 0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0010 0000 0010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...
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... TXEN SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. 2001 Microchip Technology Inc. PIC18C601/801 bit TXIF (PIR registers) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE, and cannot be cleared in software ...
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... FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit DS39541A-page 188 Bit 1 Bit 2 Bit 7 Bit 0 Word 1 bit0 bit2 bit1 Advance Information Bit 1 Bit 7 Word 2 ’1’ bit6 bit7 2001 Microchip Technology Inc. ...
Page 189
... RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’. 2001 Microchip Technology Inc. PIC18C601/801 3. Ensure bits CREN and SREN are clear interrupts are desired, set enable bit RCIE. ...
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... BOR RESETS RBIF 0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 -000 0000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 TX9D 0000 0010 0000 0010 0000 0000 0000 0000 2001 Microchip Technology Inc. ...
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... SREN RCREG USART Receive Register TXSTA CSRC TX9 TXEN SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception. 2001 Microchip Technology Inc. PIC18C601/801 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF ...
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... PIC18C601/801 NOTES: DS39541A-page 192 Advance Information 2001 Microchip Technology Inc. ...
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... CONVERTER (A/D) MODULE The analog-to-digital (A/D) converter module has 8 inputs for the PIC18C601 devices and 12 for the PIC18C801 devices. This module has the ADCON0, ADCON1, and ADCON2 registers. The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number. ...
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... D 0110 D 0111 D 1000 D 1001 D 1010 D 1011 D 1100 D 1101 D 1110 D 1111 A = Analog input Shaded cells = Additional A/D channels available on PIC18C801 devices. Legend Readable bit - n = Value at POR DS39541A-page 194 U-0 R/W-0 R/W-0 R/W-0 — VCFG1 VCFG0 PCFG3 A A REF REF A A VDD ...
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... The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. 2001 Microchip Technology Inc. U-0 U-0 U-0 U-0 — ...
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... DS39541A-page 196 CHS3:CHS0 V IN (Input voltage VCFG0 AV SS VCFG1 Advance Information 0111 RF2/AN7 0110 RF1/AN6 0101 RF0/AN5 0100 RA5/AN4 0011 RA3/AN3/V + REF 0010 RA2/AN2/V - REF 0001 RA1/AN1 0000 RA0/AN0 1011 (1) RH7/AN11 1010 (1) RH6/AN10 1001 (1) RH5/AN9 1000 (1) RH4/AN8 2001 Microchip Technology Inc. ...
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... LEAKAGE various junctions R = interconnect resistance sampling switch C = sample/hold capacitance (from DAC) HOLD R = sampling switch resistance SS 2001 Microchip Technology Inc. PIC18C601/801 2. Configure A/D interrupt (if desired): • Clear ADIF bit • Set ADIE bit • Set GIE bit 3. Wait the required acquisition time. 4. ...
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... T based on the following application system assumptions: . The sampling C HOLD Rs Conversion Error V DD Temperature V HOLD (-Tc HOLD ln(1/2047 ln(1/2047) S Advance Information the minimum acquisition time, . This calculation is ACQ = 120 pF = 2.5 k 1/2 LSb = 5V Rss = (system max time = 0 2001 Microchip Technology Inc. ...
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... For faster conversion times, the selection of another clock source is recommended. 4: For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D accuracy may be out of specification. 5: This column is for the LC devices only. 2001 Microchip Technology Inc. PIC18C601/801 17.3 Configuring Analog Port Pins The ADCON1, TRISA, TRISF and TRISH registers control the operation of the A/D port pins ...
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... If the A/D module is not enabled (ADON is cleared), the “special event trigger” will be ignored by the A/D mod- ule, but will still reset the Timer1 (or Timer3) counter. CYCLES Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Advance Information 2001 Microchip Technology Inc. ...