PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 234

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
DAW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example1:
Example 2:
DS39541A-page 234
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
Q1
WREG
C
DC
WREG
C
DC
WREG
C
DC
WREG
C
DC
register WREG
=
=
=
=
=
=
=
=
=
=
=
=
Decimal Adjust WREG Register
[label] DAW
None
If [WREG<3:0> >9] or [DC = 1] then
(WREG<3:0>) + 6
else
(
If [WREG<7:4> >9] or [C = 1] then
(
else
(WREG<7:4>)
C
DAW adjusts the eight-bit value in
WREG resulting from the earlier
addition of two variables (each in
packed BCD format) and produces a
correct packed BCD result.
1
1
DAW
Read
WREG<3:0>)
WREG<7:4>) + 6
Q2
0000
0A5h
0
0
05h
1
0
0CEh
0
0
34h
1
0
0000
Process
Data
Q3
WREG<7:4>;
W<3:0>;
0000
W<3:0>;
WREG<7:4>;
Advance Information
WREG
Write
Q4
0111
DECF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
CNT
Z
CNT
Z
Q1
=
=
=
=
register ’f’
Decrement f
[ label ] DECF f [,d [,a]]
0
d
a
(f) – 1
C,DC,N,OV,Z
Decrement register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the result is stored back in register 'f'
(default). If ’a’ is 0, the Access Bank
will be selected, overriding the BSR
value. If ’a’ is 1, the Bank will be
selected as per the BSR value.
1
1
DECF
Read
0000
Q2
01h
0
00h
1
f
[0,1]
[0,1]
2001 Microchip Technology Inc.
255
dest
CNT
01da
Process
Data
Q3
ffff
destination
Write to
Q4
ffff