PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 43

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

4.1.2
When configured as Program Memory, Boot RAM can
be used as a temporary “Boot Loader” for programming
purposes. If an external memory device is used as pro-
gram memory, any updates performed by the user pro-
gram will have to be performed in the “Boot RAM”,
because the user program cannot program and fetch
from external memory, simultaneously.
A typical boot loader execution and external memory
programming sequence would be as follows:
• The boot loader program is transferred from the
• Once the “boot loader” program is loaded into
• Jump to beginning of Boot code in Boot RAM.
• Boot loader program performs the necessary
• When the boot loader program is finished pro-
4.2
The return address stack allows any combination of up to
31 program calls and interrupts to occur. The PC (Pro-
gram Counter) is pushed onto the stack when a PUSH,
CALL or RCALL instruction is executed, or an interrupt is
acknowledged. The PC value is pulled off the stack on a
RETURN, RETLW or a RETFIE instruction. PCLATU and
PCLATH are not affected by any of the return instructions.
The stack operates as a 31-word by 21-bit stack memory
and a five-bit stack pointer, with the stack pointer initial-
ized to 00000b after all RESETS. There is no RAM asso-
ciated with stack pointer 00000b. This is only a RESET
value. During a CALL type instruction, causing a push
onto the stack, the stack pointer is first incremented and
the RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction, causing a pop from the stack, the contents of
the RAM location indicated by the STKPTR is transferred
to the PC and then the stack pointer is decremented.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the data on the top of the stack is readable and writable
through SFR registers. Status bits STKOVF and
STKUNF in STKPTR register, indicate whether stack
over/underflow has occurred or not.
external program memory to the last 2 banks of
data RAM by TBLRD and MOVWF instructions.
internal memory and verified, open combination
lock and set PGRM bit to configure the data RAM
into program RAM.
Program execution begins in Boot RAM to begin
programming the external memory. System bus
changes to an inactive state.
external TBLWT and TBLWRD instructions to
perform programming functions.
gramming external memory, jump to known valid
external program memory location and clear
PGRM bit in MEMCON register to set Boot RAM
as data memory, or reset the part.
2001 Microchip Technology Inc.
Return Address Stack
BOOT LOADER
Advance Information
4.2.1
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, allow
access to the contents of the stack location indicated by
the STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user should disable the global interrupt enable bits
during this time to prevent inadvertent stack operations.
4.2.2
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR. Any subsequent push operation that causes
stack overflow will be ignored.
The action that takes place when the stack becomes
full, depends on the state of STVREN (stack overflow
RESET enable) configuration bit in CONFIG4L regis-
ter. Refer to Section 4.2.4 for more information. If
STVREN is set (default), stack over/underflow will set
the STKFUL bit, and reset the device. The STKFUL bit
will remain set and the stack pointer will be set to 0.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31. All
subsequent push attempts will be ignored and
STKPTR remains at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software, or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appro-
priate actions can be taken.
TOP-OF-STACK ACCESS
RETURN STACK POINTER
(STKPTR)
PIC18C601/801
DS39541A-page 43