PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 245

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

RCALL
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
operation
Decode
No
PC =
PC =
TOS =
Q1
Read literal
Push PC to
Address (HERE)
Address (Jump)
Address (HERE+2)
operation
Relative Call
[ label ] RCALL
-1024
(PC) + 2
(PC) + 2 + 2n
None
Subroutine call with a jump up to 1K
from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the new
address will be PC+2+2n. This
instruction is a two-cycle instruction.
1
2
HERE
stack
1101
No
Q2
’n’
n
RCALL
1nnn
TOS,
operation
1023
Process
Data
No
Q3
PC
Jump
n
nnnn
Write to PC
Advance Information
operation
No
Q4
nnnn
RESET
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
After Instruction
Decode
Registers =
Flags*
Q1
PIC18C601/801
=
Reset
[ label ]
None
Reset all registers and flags that are
affected by a MCLR Reset.
All
This instruction provides a way to
execute a MCLR Reset in software.
1
1
RESET
reset
Start
0000
Q2
Reset Value
Reset Value
RESET
0000
operation
No
Q3
DS39541A-page 245
1111
operation
No
Q4
1111