PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 162

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
15.4.2
The addressing procedure for the I
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I
consists of all 0’s with R/W = 0.
The general call address is recognized (enabled) when
the General Call Enable (GCEN) bit is set (SSPCON2
register). Following a START bit detect, eight bits are
shifted into the SSPSR and the address is compared
against the SSPADD. It is also compared to the general
call address and fixed in hardware.
FIGURE 15-9:
DS39541A-page 162
GCEN
SSPOV
SDA
SCL
SSPIF
BF
GENERAL CALL ADDRESS
SUPPORT
S
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS)
1
2
General Call Address
2
C bus is such that
3
2
C protocol. It
4
Advance Information
5
6
7
R/W = 0
8
If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF bit is set (eighth bit),
and on the falling edge of the ninth bit (ACK bit), the
SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT register). If the general call address
is sampled when the GCEN bit is set and while the
slave is configured in 10-bit address mode, then the
second half of the address is not necessary. The UA bit
will not be set, and the slave will begin receiving data
after the Acknowledge (Figure 15-9).
ACK
Address is compared to General Call Address
after ACK, set interrupt
9
D7
1
D6
2
Cleared in software
SSPBUF is read
Receiving Data
D5
3
D4
4
D3
5
2001 Microchip Technology Inc.
D2
6
D1
7
D0
8
ACK
9
’0’
’1’