PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 51

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

EXAMPLE 4-5:
FIGURE 4-7:
UNLOCK_N_MODIFY @REG
2001 Microchip Technology Inc.
BSR<3:0>
= 0100b
= 0000b
= 0001b
= 0010b
= 0011b
= 0110b
= 1110b
= 0101b
= 1111b
COMBINATION UNLOCK MACRO EXAMPLE CODE
THE DATA MEMORY MAP FOR PIC18C801/601 (PGRM = 0)
Bank 14
Bank 15
Bank 6
Bank 0
Bank 1
Bank 4
Bank 2
Bank 3
Bank 5
to
MACRO
BCF INTCON, GIE
BSF PSPCON, CMLK1
BSF PSPCON, CMLK0
MOVWF @REG
BSF INTCON, GIE
ENDM
MOVLW 5Ah
UNLOCK_N_MODIFY OSCCON
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
FFh
00h
Data Memory Map
Access GPR’s
Access SFR’s
Read ’00h’
Advance Information
Unused
Unused
GPR
GPR
GPR
GPR
GPR
GPR
; Disable interrupts
; Modify given register
; Enable interrupts
; Preload WREG for OSCCON register
; Modify OSCCON
000h
07Fh
080h
0FFh
100h
1FFh
200h
2FFh
300h
3FFh
400h
4FFh
500h
5FFh
EFFh
F00h
F7Fh
F80h
FFFh
PIC18C601/801
When a = 0,
the BSR is ignored and this
Access RAM bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The next 128 bytes are Special
Function Registers (from
Bank 15).
When a = 1,
the BSR is used to specify
the RAM location that the
instruction uses.
Access RAM Bank
Access Bank High
Access Bank Low
(GPR’s)
(SFR’s)
DS39541A-page 51
00h
7Fh
FFh
80h