PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 285

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

FIGURE 22-15:
TABLE 22-14: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
70
71
71A
72
72A
73
73A
74
75
76
77
78
79
80
83
Note 1: Requires the use of parameter # 73A.
Param
2001 Microchip Technology Inc.
No.
Note: Refer to Figure 22-4 for load conditions.
(CKP = 0)
(CKP = 1)
SDI
SDI
SS
SCK
SCK
SDO
2: Only if parameter #s 71A and 72A are used.
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
T
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ
TscR
TscF
TscH2doV,
TscL2doV
TscH2ssH,
TscL2ssH
Symbol
B
2
B
SS to SCK or SCK input
SCK input high time
(Slave mode)
SCK input low time
(Slave mode)
Setup time of SDI data input to SCK edge
Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5T
Hold time of SDI data input to SCK edge
SDO data output rise time
SDO data output fall time
SS to SDO output hi-impedance
SCK output rise time
(Master mode)
SCK output fall time (Master mode)
SDO data output valid after SCK
edge
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
70
after SCK edge
80
71
73
MSb In
MSb
Characteristic
74
72
Advance Information
75, 76
Continuous
Single Byte
Continuous
Single Byte
PIC18C601/801
PIC18LC601/801
PIC18C601/801
PIC18LC601/801
PIC18C601/801
PIC18LC601/801
Bit6 - - - - - -1
Bit6 - - - -1
78
79
1.25T
1.25T
1.5T
PIC18C601/801
LSb
79
78
Min
100
T
100
CY
CY
LSb In
40
40
—
—
10
—
—
—
CY
CY
CY
+ 40
+ 40
+ 30
+ 30
83
77
Max Units
100
25
45
25
50
25
45
25
50
—
—
—
—
—
—
—
—
—
DS39541A-page 285
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 2)
Conditions