PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 235

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
Q1
Q1
PC
CNT
If CNT
If CNT
Q1
PC =
PC =
=
=
=
register ’f’
operation
operation
operation
Decrement f, skip if 0
[ label ] DECFSZ f [,d [,a]]
0
d
a
(f) – 1
skip if result = 0
None
The contents of register 'f' are decre-
mented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result
is placed back in register 'f' (default).
If the result is 0, the next instruction,
which is already fetched, is dis-
carded, and a NOP is executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE+2)
f
[0,1]
[0,1]
by a 2-word instruction.
255
dest,
11da
operation
operation
operation
DECFSZ
GOTO
Process
Data
No
No
No
Q3
Q3
Q3
ffff
CNT
LOOP
destination
operation
operation
operation
Advance Information
Write to
No
No
No
Q4
Q4
Q4
ffff
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Example:
Before Instruction
After Instruction
operation
operation
operation
Decode
TEMP
TEMP
If TEMP
If TEMP
No
No
No
Q1
Q1
Q1
PC
PC
PIC18C601/801
register ’f’
operation
operation
operation
Decrement f, skip if not 0
[label] DCFSNZ f [,d [,a]]
0
d
a
(f) – 1
skip if result
None
The contents of register 'f' are decre-
mented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the result
is placed back in register 'f' (default).
If the result is not 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOP is executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
f
[0,1]
[0,1]
by a 2-word instruction.
255
=
=
=
=
=
dest,
DCFSNZ
:
:
11da
operation
operation
operation
?
TEMP - 1,
0;
Address (ZERO )
0;
Address (NZERO)
Process
Data
0
No
No
No
Q3
Q3
Q3
DS39541A-page 235
ffff
TEMP
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff