PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 131

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

11.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON register).
FIGURE 11-1:
Note:
2001 Microchip Technology Inc.
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain.
T13CKI/T1OSO
Timer1 Operation
When Timer1 is configured in an Asyn-
chronous mode, care must be taken to
make sure that there is no incoming pulse
while Timer1 is being turned off. If there is
an incoming pulse while Timer1 is being
turned off, Timer1 value may become
unpredictable.
If an application requires that Timer1 be
turned off and if it is possible that Timer1
may receive an incoming pulse while being
turned off, synchronize the external clock
first, by clearing the T1SYNC bit of register
T1CON. Please note that this may cause
Timer1 to miss up to one count.
TMR1IF
Overflow
Interrupt
Flag Bit
T1OSI
TIMER1 BLOCK DIAGRAM
T1OSC
TMR1H
TMR1
T1OSCEN
Enable
Oscillator
TMR1L
Advance Information
(1)
CLR
Clock
Internal
F
OSC
/4
TMR1ON
CCP Special Event Trigger
On/Off
When TMR1CS is clear, Timer1 increments every
instruction cycle. When TMR1CS is set, Timer1 incre-
ments on every rising edge of the external clock input
or the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is set),
the RC1/T1OSI and RC0/T1OSO/T1CKI pins become
inputs. That is, the TRISC<1:0> value is ignored.
Timer1 also has an internal “RESET input”. This RESET
can be generated by the CCP module (Table 14.0).
TMR1CS
1
0
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
PIC18C601/801
0
1
2
Synchronized
Clock Input
SLEEP Input
Synchronize
det
DS39541A-page 131