PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 313

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

SSP .................................................................................. 149
SSP Module
SSPCON1 Register ......................................................... 151
SSPCON2 Register ......................................................... 152
SSPOV ............................................................................ 167
SSPSTAT Register .......................................................... 150
SUBFWB ................................................................ 250
SUBLW ............................................................................ 251
SUBWF ............................................................................ 252
SUBWFB ......................................................................... 253
SWAPF ............................................................................ 254
Synchronous Serial Port. See SSP
T
Table Pointer Register ....................................................... 74
Table Read ........................................................................ 75
Table Read/Write Control Registers .................................. 74
Table Write ........................................................................ 77
Table Writes
TBLRD ............................................................................. 255
TBLWT ............................................................................. 256
Timer0 .............................................................................. 127
Timer1 .............................................................................. 130
2001 Microchip Technology Inc.
Block Diagram
Block Diagram (SPI Mode) ...................................... 153
I
SPI Mode ................................................................. 153
SPI Mode. See SPI
SSPBUF .................................................................. 155
SSPCON1 ............................................................... 151
SSPCON2 ............................................................... 152
SSPSR .................................................................... 155
SSPSTAT ................................................................ 150
TMR2 Output for Clock Shift ........................... 135
SPI Master Mode ..................................................... 155
SPI Slave Mode ....................................................... 156
R/W Bit .................................................................... 160
16-bit External
8-bit External ............................................................. 78
Long Writes ............................................................... 83
Associated Registers ............................................... 129
Block Diagram
Clock Source Edge Select (T0SE Bit) ..................... 129
Clock Source Select (T0CS Bit) .............................. 129
Interrupt ................................................................... 101
Overflow Interrupt .................................................... 129
Prescaler. See Prescaler, Timer0
T0CON Register ...................................................... 127
Timing Diagram ....................................................... 281
Associated Registers ............................................... 134
Block Diagram ......................................................... 131
Oscillator ......................................................... 130
Overflow Interrupt ........................................... 130
2
C Mode. See I
SPI Mode ......................................................... 153
16-bit Word Write Mode ..................................... 81
Byte Select Mode .............................................. 82
Byte Write Mode ................................................ 80
16-bit Mode ...................................................... 128
8-bit Mode ........................................................ 128
16-bit R/W Mode .............................................. 132
2
C
Advance Information
,
,
,
,
136
251
133
133
Timer2
Timer3 ............................................................................. 137
Timing Diagrams
Prescaler. See Prescaler, Timer1
Special Event Trigger (CCP) ...........................133
T1CON Register ...................................................... 130
Timing Diagram ....................................................... 281
TMR1H Register ..................................................... 130
TMR1L Register ...................................................... 130
TMR3L Register ...................................................... 137
Associated Registers .............................................. 136
Block Diagram ......................................................... 136
Postscaler. See Postscaler, Timer2
PR2 Register ...................................................135
Prescaler. See Prescaler, Timer2
SSP Clock Shift ...............................................135
T2CON Register ...................................................... 135
TMR2 Register ........................................................ 135
TMR2 to PR2 Match Interrupt ................ 135
Associated Registers .............................................. 139
Block Diagram ......................................................... 138
Oscillator .........................................................137
Overflow Interrupt ............................................137
Special Event Trigger (CCP) ................................... 139
T3CON Register ...................................................... 137
TMR3H Register ..................................................... 137
Acknowledge Sequence Timing .............................. 170
Baud Rate Generator with Clock Arbitration ........... 165
BRG Reset Due to SDA Collision ........................... 174
Bus Collision
Bus Collision During a RESTART Condition
Bus Collision During a RESTART Condition
Bus Collision During a START Condition
Bus Collision During a STOP Condition .................. 176
Bus Collision for Transmit and Acknowledge .......... 172
I
I
I
I
Master Mode Transmit Clock Arbitration ................. 171
Repeated START Condition .................................... 166
Slave Synchronization ............................................. 156
Slow Rise Time ......................................................... 33
SPI Mode Timing (Master Mode) SPI Mode
SPI Mode Timing (Slave Mode with CKE = 0) ........ 157
SPI Mode Timing (Slave Mode with CKE = 1) ........ 157
STOP Condition Receive or Transmit ..................... 170
Time-out Sequence on Power-up ............................. 32
USART Asynchronous Master Transmission .......... 184
USART Asynchronous Reception ........................... 186
USART Synchronous Reception ............................. 189
USART Synchronous Transmission ........................ 188
Wake-up from SLEEP via Interrupt ......................... 213
2
2
2
2
C Bus Data ........................................................... 289
C Master Mode First START Bit Timing ............... 165
C Master Mode Reception Timing ........................ 169
C Master Mode Transmission Timing ................... 168
16-bit R/W Mode ............................................. 138
START Condition Timing ................................ 173
Master Mode Timing Diagram ......................... 155
(Case 1) .................................................. 175
(Case 2) .................................................. 175
(SCL = 0) ................................................. 174
PIC18C601/801
DS39541A-page 313
,
136
,
,
,
,
,
,
144
146
136
146
139
139