PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 83

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

6.4
Long writes will not be supported on the PIC18C601/801
to program FLASH configuration memory. The configu-
ration locations can only be programmed in ICSP mode.
6.5
The Table Reads and Writes have the capability to
insert wait states when accessing external memory.
These wait states only apply to the execution of a Table
Read or Write to external memory and not to instruction
fetches out of external memory. The guidelines pre-
sented in Section 5.0 must be followed to select the
proper memory speed grade for the device operating
frequency.
FIGURE 6-11:
2001 Microchip Technology Inc.
Long Writes
External Wait Cycles
Apparent Q
AD<7:0>
A<19:8>
Actual Q
ALE
BA0
OE
EXTERNAL INTERFACE TIMING (8-BIT MODE)
Q1
Q1
Opcode Fetch
from 007556h
ABh
MOVLW 55h
Q2
Q2
03Ah
55h
Q3
Q3
Q4
Q4
0Eh
Q1
Q1
Advance Information
33h
Q2
Q2
CCFh
Q3
Q3
from 199E67h
Table Read
of 92h
Q4
Q4
Q4
Q1
The WAIT<1:0> bits in the MEMCON register will select
0, 1, 2, or 3 extra T
The wait will occur on Q4.
The default setting of the wait on power-up is to assert
a maximum wait of 3T
memories will work in Microprocessor mode immedi-
ately after RESET.
Figure 6-11 shows 8-bit external bus timing for a Table
Read with 2 wait cycles. Figure 6-12 shows 16-bit
external bus timing for a Table Read with 1 wait cycle.
Q4
Q2
Q4
Q3
2T
Q4
Q4
PIC18C601/801
CY
Wait
CY
Q4
Q1
92h
CY
cycles per TBLRD/TBWLT cycle.
Q4
Q2
cycles. This insures that slow
Q4
Q3
Q4
Q4
DS39541A-page 83