PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 71

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

5.4.1
CS1 is enabled by writing a value other than 00h into
either the CSEL2 register, or the CSELIO register. If
both of the chip select registers are programmed to
00h, the CS1 signal is not enabled and the RF5 pin is
configured as I/O.
CS1 is low for all addresses in which CS2 and CSELIO
are high. Therefore, if CSEL2 = 20h and CSELIO = 80h,
then the CS1 signal will be low for the address that falls
between 000000h and (2000h x 20h) - 1 = 03FFFFh.
CS1 will always be low for the lower 8K of program
memory. Figure 5-9 shows an example address map for
CS1.
5.4.2
CS2 is enabled for program memory accesses, starting
at the address derived by the 8-bit value contained in
CSEL2. For example, if the value contained in the
CSEL2 register is 80h, then the CS2 signal will be
asserted low whenever the address is greater than or
equal to 2000h x 80h = 100000h.
FIGURE 5-9:
2001 Microchip Technology Inc.
CSEL2 = FFh (DEFAULT)
CSELIO = FFh (DEFAULT)
PROGRAM MEMORY
CHIP SELECT 1 (CS1)
CHIP SELECT 2 (CS2)
= CS1 ACTIVE
EXAMPLE CONFIGURATION ADDRESS MAP FOR CS1, CS2, AND CSIO
000000h
1FFDFFh
1FFE00h
1FFFFFh
= CS2 ACTIVE
Advance Information
CSEL2 = 80h
CSELIO = 00h
PROGRAM MEMORY
A 00h value in the CSEL2 register will disable the CS2
signal and will configure the RF4 pin as I/O. Figure 5-9
shows an example address map for CS2.
5.4.3
CSIO is enabled for a fixed 8K address range starting
at the address defined by the 8-bit value contained in
CSELIO. If, for instance, the value contained in the
CSELIO register is 80h, then the CSIO signal will be
low for the address range between 100000h and
101FFFh.
If the 8K address block overlaps the address range
specified in the CSEL2 register, the CSIO signal will be
low, and the CS2 signal will be high, for that region.
A 00h value in the CSELIO register will disable the
CSIO signal and will configure the RF3 pin as I/O.
Figure 5-9 shows an example address map for CSIO.
= CSIO ACTIVE
000000h
0FFFFFh
100000h
1FFDFFh
1FFE00h
1FFFFFh
CHIP SELECT I/O (CSIO)
PIC18C601/801
CSEL2 = 20h
CSELIO = 80h
PROGRAM MEMORY
= NO CHIP SELECT ACTIVE
INTERNAL EXECUTION IF
PGRM = 1
DS39541A-page 71
000000h
03FFFFh
040000h
0FFFFFh
100000h
101FFFh
102000h
1FFDFFh
1FFE00h
1FFFFFh