PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 190

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
16.4
Synchronous Slave mode differs from the Master
mode, in that the shift clock is supplied externally at the
RC6/TX/CK pin (instead of being supplied internally in
Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA register).
16.4.1
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
When setting up a Synchronous Slave Transmission,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
DS39541A-page 190
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will be set.
If enable bit TXIE is set, the interrupt will wake the
chip from SLEEP. If the global interrupt is enabled,
the program will branch to the interrupt vector.
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
USART Synchronous Slave Mode
USART SYNCHRONOUS SLAVE
TRANSMIT
USART Transmit Register
Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
CSRC
SPEN
Bit 7
—
—
—
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
Advance Information
INT0IE
CREN
SYNC
TXIF
TXIE
TXIP
Bit 4
ADDEN
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
TMR0IF
CCP1IF
CCP1IE
CCP1IP
BRGH
FERR
Bit 2
16.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a "don’t care" in Slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector.
When setting up a Synchronous Slave Reception,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
Bit 1
USART SYNCHRONOUS SLAVE
RECEPTION
TMR1IF
TMR1IE
TMR1IP
RX9D
TX9D
RBIF
Bit 0
2001 Microchip Technology Inc.
0000 000x
-000 0000
-000 0000
-000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
Value on
POR,
BOR
Value on all
0000 000u
-000 0000
-000 0000
-000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
RESETS
other