PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 212

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
19.3
Power-down mode is entered by executing a SLEEP
instruction.
Upon entering into Power-down mode, the following
actions are performed:
1.
2.
3.
4.
5.
To achieve lowest current consumption, follow these
steps before switching to Power-down mode:
1.
2.
3.
4.
5.
The MCLR pin must be at a logic high level (V
19.3.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
The following peripheral interrupts can wake the device
from SLEEP:
4.
5.
6.
7.
8.
9.
10. USART RX or TX (Synchronous Slave mode).
11. A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
DS39541A-page 212
Watchdog Timer is cleared and kept running.
PD bit in RCON register is cleared.
TO bit in RCON register is set.
Oscillator driver is turned off.
I/O ports maintain the status they had before the
SLEEP instruction was executed.
Place all I/O pins at either V
ensure no external circuitry is drawing current
from I/O pin.
Power-down A/D and external clocks.
Pull all hi-impedance inputs to high or low,
externally.
Place T0CKI at V
Current consumption by PORTB on-chip pull-
ups should be taken into account and disabled,
if necessary.
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change, or a
peripheral interrupt.
TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
TMR3 interrupt. Timer3 must be operating as
an asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
MSSP (START/STOP) bit detect interrupt.
MSSP transmit or receive in Slave mode
(SPI/I
Power-down Mode (SLEEP)
2
C).
WAKE-UP FROM SLEEP
SS
or V
DD
.
DD
or V
Advance Information
SS
IHMC
and
).
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
19.3.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If an interrupt condition (interrupt flag bit and inter-
• If the interrupt condition occurs during or after
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
rupt enable bits are set) occurs before the execu-
tion of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
the execution of a SLEEP instruction, the device
will immediately wake-up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
WAKE-UP USING INTERRUPTS
2001 Microchip Technology Inc.