NH82810 S L7XK Intel, NH82810 S L7XK Datasheet
NH82810 S L7XK
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... R ® Intel 810E Chipset: 82810E Graphics and Memory Controller Hub (GMCH) Datasheet September 2000 Order Number: 290676-002 ...
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... Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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... R Contents 1. Overview.....................................................................................................................................11 ® 1.1. The Intel 1.2. GMCH Overview ............................................................................................................13 1.3. Host Interface.................................................................................................................14 1.4. System Memory Interface ..............................................................................................14 1.5. Display Cache Interface .................................................................................................14 1.6. Hub Interface..................................................................................................................14 1.7. GMCH Graphics Support ...............................................................................................15 1.7.1. 1.8. System Clocking ............................................................................................................16 1.9. References.....................................................................................................................16 2. Signal Description.......................................................................................................................17 2.1. Host Interface Signals ....................................................................................................18 2.2. ...
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... Intel 82810E (GMCH) 3.4.12. 3.4.13. 3.4.14. 3.4.15. 3.4.16. 3.4.17. 3.4.18. 3.4.19. 3.4.20. 3.4.21. 3.5. Graphics Device Registers (Device 1)........................................................................... 49 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 3.5.7. 3.5.8. 3.5.9. 3.5.10. 3.5.11. 3.5.12. 3.5.13. 3.5.14. 3.5.15. 3.5.16. 3.5.17. 3.5.18. 3.5.19. 3.5.20. 3.5.21. ...
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... Hardware Motion Compensation .................................................................95 Hardware Cursor..........................................................................................96 Overlay Engine.............................................................................................96 Display .........................................................................................................96 Flat Panel Interface / 1.8V TV-Out Interface................................................99 DDC (Display Data Channel) .....................................................................100 Specifications Supported ...........................................................................101 Test Pattern Consideration for XOR Chain 7.............................................112 Chain [1:2, 4:7] Initialization .......................................................................113 Chain 3 Initialization ...................................................................................113 ® Intel 82810E (GMCH) 5 ...
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... Intel 82810E (GMCH) Figures ® Figure 1. Intel 810E Chipset System Block Diagram With Intel 82810E GMCH and ICH...... 12 Figure 2. GMCH Block Diagram............................................................................................... 13 Figure 3. System Memory Address Map .................................................................................. 70 Figure 4. Detailed Memory System Address Map.................................................................... 71 Figure 5 GMCH’s Graphics Register Memory Address Space ................................................ 74 Figure 6 ...
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... Added Section 4.9.2, “Resume From S3” • Updated BUFF_SC Register description (see Section 3.4.21, “BUFF_SC— System Memory Buffer Strength Control Register (Device 0)”) • Editorial changes throughout for clarity Datasheet Description ® Intel 82810E (GMCH) Date September 1999 September 2000 7 ...
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... GMCH Product Features ! Processor/Host Bus Support Optimized for the Intel Intel Pentium III processor, and Intel TM Celeron processor Supports processor 370-Pin Socket and SC242 connectors Supports 32-Bit System Bus Addressing 4 deep in-order queue deep request queue ...
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... LSCAS# LMA[11:0] LWE# LMD[31:0] Datasheet ADS# BNR# System Bus Interface HIT# System Memory Interface LCS# Display Cache Interface 82810E . ® Intel 82810E (GMCH) VSYNC HSYNC IREF Display RED Interface GREEN BLUE DDCSCL DDCSDA LTVCL LTVDA TVCLKIN/INT# Digital CLKOUT[1:0] TV BLANK# Out LTVDATA[11:0] ...
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... Intel 82810E (GMCH) 10 This page is intentionally left blank. R Datasheet ...
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... AC’97 2.1 Compliant Link for Audio and Telephony CODECs • Low Pin Count (LPC) interface • Firmware Hub (FWH) interface support • Alert On LAN* Figure 1 shows a block diagram of a typical platform based on the Intel supports processor bus frequencies of 66/100/133 MHz. Datasheet ® ...
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... Intel 82810E (GMCH) ® Figure 1. Intel 810E Chipset System Block Diagram With Intel 82810E GMCH and ICH Digital Video O ut Display Cache ( SDRAM , 100/133 nly) 2 IDE P orts Ultra ATA /66 2 USB Ports 12 ® ® Intel Pentium III Processor, ® ® ...
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... Out DDC Datasheet System Bus Interface Display Engine 3D Engine HW Motion Comp 3D Engine DAC Overlay 2D Engine HW Cursor Stretch BLT Eng Digital Video Out BLT Eng Port Hub Interface ® Intel 82810E (GMCH) Buffer System Memory Memory Interface Display Cache Memory Buffer gmch_blk2.vsd 13 ...
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... Intel 82810E (GMCH) 1.3. Host Interface The host interface of the GMCH is optimized to support the Intel ® Intel Pentium II processor, and Intel control, and data bus interfaces within a single device. The GMCH supports a 4-deep in-order queue (i.e., supports pipelining outstanding transaction requests on the host bus) . Host bus addresses are decoded by the GMCH for accesses to system memory, PCI memory and PCI I/O (via hub interface), PCI configuration space and Graphics memory ...
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... The GMCH provides a Digital Video Out interface to connect an external device to drive an autodetection of 1024x768 non-scalar DDP digital Flat Panel with appropriate EDID 1.x data. The interface has 1.8V signaling to allow it to operate at higher frequencies. This interface can also connect to a 1.8V TV-Out encoder. Datasheet ® Intel 82810E (GMCH) 15 ...
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... References • Intel 810E Chipset Design Guide. Contact your field sales representative. • PC ’99: Contact www.microsoft.com/hwdev • AGTL+ I/O Specification: Contained in the Intel • PCI Local bus Specification 2.2: Contact • ® Intel 82801AA (ICH) I/O Controller Hub Datasheet 16 ...
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... GMCH. All processor control signals follow normal convention indicates an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix. Datasheet ® Intel 82810E (GMCH) 17 ...
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... Intel 82810E (GMCH) 2.1. Host Interface Signals Signal Name CPURST# O AGTL+ HA[31:3]# I/O AGTL+ HD[63:0]# I/O AGTL+ ADS# I/O AGTL+ BNR# I/O AGTL+ BPRI# O AGTL+ DBSY# I/O AGTL+ DEFER# O AGTL+ DRDY# I/O AGTL+ HIT# I/O AGTL+ HITM# I/O AGTL+ HLOCK# ...
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... SDRAM Column Address Strobe: These signals drive the SDRAM array directly without any external buffers. Write Enable Signal: SWE# is asserted during writes to DRAM. System Memory Clock Enable: SCKE SDRAM Clock Enable is used to signal a self-refresh or power-down command to an SDRAM array when entering system suspend. ® Intel 82810E (GMCH) Description Description 19 ...
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... Intel 82810E (GMCH) 2.3. Display Cache Interface Signals Signal Name LCS# O CMOS LDQM[3:0] O CMOS LSRAS# O CMOS LSCAS# O CMOS LMA[11:0] O CMOS LWE# O CMOS LMD[31:0] I/O CMOS 2.4. Hub Interface Signals Signal Name HL[10:0] I/O HLSTRB I/O HLSTRB# I/O HUBREF I Ref HCOMP ...
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... DDCSCL and DDCSDA provides a unidirectional channel for Extended Display ID. For DDC2, DDCSCL and DDCSDA it can be used to establish a bi-directional 2 channel based protocol. The host can request Extended Display ID or Video Display Interface information over the DDC2 channel. CRT Monitor DDC Interface Data: ® Intel 82810E (GMCH) Description TM “Display Data 21 ...
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... Intel 82810E (GMCH) 2.6. Digital Video Output Signals/TV-Out Pins Signal Name TVCLKIN/INT# CLKOUT[1:0] BLANK# LTVDATA[11:0] TVVSYNC TVHSYNC LTVCL LTVDA 22 Type I Low Voltage TV Clock In (TV-Out Mode): In 1.8V TV-Out usage, the 1.8V TVCLKIN pin functions as a pixel clock input to the GMCH from the TV encoder ...
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... Receive Clock: LRCLK is a display cache clock used to clock the input buffers of the GMCH. Display Interface Clock: DCLKREF MHz clock generated by an external clock synthesizer to the GMCH. Hub Interface Clock: 66 MHz hub interface clock generated by an external clock synthesizer. ® Intel 82810E (GMCH) Description Description 23 ...
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... Intel 82810E (GMCH) 2.9. Miscellaneous Interface Signals Signal Name GTLREFA GTLREFB RESET# 2.10. Power-Up/Reset Strap Options Table 1 list power-up options that are loaded into the 82810E GMCH during cold reset. Table 1. Power Up Options Signal LMD[31] LMD[30] LMD[29] LMD[28] LMD[13] Table 2. Host Frequency Strappings ...
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... Registers configuration space of the Host-hub interface Bridge/DRAM Controller and the internal graphics device entities that are marked either "Reserved” or Intel Reserved”. When a “Reserved” register location is read, a random value can be returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Registers that are marked as “Reserved” must not be modified by system software. Writes to “ ...
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... Intel 82810E (GMCH) 3.2. PCI Configuration Space Access The GMCH and the ICH are physically connected via the hub interface. From a configuration standpoint, the hub interface connecting the GMCH and the ICH is logically PCI bus #0. All devices internal to the GMCH and ICH appear PCI bus #0. The system primary PCI expansion bus is physically attached to the ICH and, from a configuration standpoint, appears as a hierarchical PCI bus behind a PCI-to-PCI bridge ...
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... The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of CONFIG_ADDRESS register that can only be accessed as a DWord. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field). Datasheet ® Intel 82810E (GMCH) 27 ...
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... Intel 82810E (GMCH) 3.3. I/O Mapped Registers GMCH contains two registers that reside in the processor I/O address space − the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion of configuration space is visible through the Configuration Data window. CONFIG_ADDRESS ...
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... CONFIG_DATA is determined by the contents of CONFIG_ADDRESS. Bit 31:0 Configuration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, any I/O reference that falls in the CONFIG_DATA I/O space will be mapped to configuration space using the contents of CONFIG_ADDRESS. Datasheet Descriptions 0CFCh 00000000h Read/Write 32 bits Descriptions ® Intel 82810E (GMCH) 29 ...
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... Intel 82810E (GMCH) 3.4. Host-Hub Interface Bridge/DRAM Controller Device Registers (Device 0) Table 3 shows the GMCH configuration space for device #0. Table 3. GMCH PCI Configuration Space (Device 0) Address Offset 00–01h VID 02–03h DID 04–05h PCICMD 06–07h PCISTS 08h RID 09h 0Ah ...
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... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. Intel VID = 8086h. DID Device Identification Register (Device 0) 3.4.2. Address Offset: ...
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... Intel 82810E (GMCH) PCICMD PCI Command Register (Device 0) 3.4.3. Address Offset: Default: Access: Size This 16-bit register provides basic control over the GMCH PCI0 (i.e., Hub-Interface) interface’s ability to respond to Hub Interface cycles Addr/Data Parity Stepping ...
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... NO CAPPTR. 3:0 Reserved. Datasheet 06–07h 0080h Read Only, Read/Write Clear 16 bits Recog Rec Sig Target Mast Abort Target Abort Sta Sta Abort Sta (HW=0) (HW= Reserved Cap List (HW=0) Descriptions ® Intel 82810E (GMCH DEVSEL# Timing Data Par (HW=00) Detected (HW=0) Reserved ...
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... Intel 82810E (GMCH) RID Revision Identification Register (Device 0) 3.4.5. Address Offset: Default Value: Access: Size: This register contains the revision number of the GMCH Device 0. These bits are read only and writes to this register have no effect. Bit 7:0 Revision Identification Number ...
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... BIOS during boot-up. Once written, this register becomes read only. This register can only be cleared by a reset. Datasheet 0Dh 00h Read Only 8 bits Descriptions 0Eh 00h Read Only 8 bits Descriptions 2C–2Dh 0000h Read/Write Once 16 bits Description ® Intel 82810E (GMCH) 35 ...
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... Intel 82810E (GMCH) 3.4.11. SIDSubsystem Identification Register (Device 0) Offset: Default: Access: Size: Bit 15:0 Subsystem ID—R/WO. This value is used to identify a particular subsystem. This field should be programmed by BIOS during boot-up. Once written, this register becomes read only. This Register can only be cleared by a reset ...
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... PAM register Disable. The “CD Hole” region is controlled by bits 3 & the PAM Register. Datasheet 50h 60h Read/Write, Read Only 8 bits Reserved Local DRAM Pg Memory Closing Frequency Select Description ® Intel 82810E (GMCH Reserved D8 Hole Enable Policy 0 CD Hole Enable 37 ...
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... Intel 82810E (GMCH) 3.4.14. PAMR—Programmable Attributes Register (Device 0) Address Offset: Default Value: Access: Size: The Programmable Attributes Register controls accesses to the memory range 000C0000h to 000FFFFFh. 7 Seg_F Access Control Bit 7:6 Seg_F Access Control. This field controls accesses to 000F0000 to 000FFFFF. ...
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... DIMM 1 Population Bit 7:4 DIMM 1 Population. This field indicates the population of DIMM 1. (See table below ) 3:0 DIMM 0 Population. This field indicates the population of DIMM 0. (See table below ) Datasheet 52h 00h Read/Write (read only) 8 bits 4 3 DIMM 0 Population Description ® Intel 82810E (GMCH ...
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... Intel 82810E (GMCH) Table 4. Programming DRAM Row Population Register Fields Field Value (Hex Size Technology Population 0 MB Empty 8 MB 16Mb 4x(1Mx16 16Mb 4x(1Mx16 16Mb 8x(2Mx8 16Mb 8x(2Mx8 16Mb 8x(2Mx8 64Mb 4x(4Mx16 128Mb 2x(4Mx32 Mixed 4x(4Mx16 64Mb 4x(4Mx16 Mixed 2x(4Mx32 64Mb ...
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... DRAM Cycle Time ( DCT ). This bit controls the number of SCLKs for an access cycle. Bit4 Intel Reserved. 2 CAS# Latency (CL). This bit controls the number of CLKs between when a read command is sampled by the SDRAMs and when the GMCH samples read data from the SDRAMs SCLKs (Default) ...
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... Intel 82810E (GMCH) Bit 1 SDRAM RAS# to CAS# Delay (SRCD). This bit controls the number of SCLKs from a Row Activate command to a read or write command SCLKs (Default SCLKs 0 SDRAM RAS# Precharge (SRP). This bit controls the number of SCLKs for RAS# precharge SCLKs (Default SCLKs FCHC ...
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... TSEG is Enabled as 512 KB and HSEG is Conditionally Enabled 11 = TSEG is Enabled and HSEG is Conditionally Enabled Once D_LCK is set, these bits becomes read only. Datasheet 70h 00h Read/Write 8 bits Upper SMM Select Lower SMM Select Description ® Intel 82810E (GMCH SMM E_SMRA Space M_ERR Locked 43 ...
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... Intel 82810E (GMCH) Bit 3:2 Lower SMM Select ( LSMM ). This field controls the definition of the A&B segment SMM space segment disabled segment enabled as General System RAM segment enabled as SMM Code RAM Shadow. Only SMM Code Reads can access DRAM in the AB segment, SMM Data operations and all Non-SMM Operations go to either the internal Graphics Device or are broadcast on hub interface ...
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... Locked. Bits 7:3 of the MISCC register are read-only. Once this bit is set can only be cleared hardware reset Not locked. 2:1 Reserved. 0 Graphics Display Cache Window Size Select (default MB. See GMADR Register (Device 1). Datasheet 72–73h 0000h Read/Write Reserved Write Power Throttle Control Description ® Intel 82810E (GMCH Reserved GFX Local Mem Win Size Sel 45 ...
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... Intel Reserved Immediate (must be 1) Blit Enable Bit 7 Intel Reserved. This Bit must be programmed not program Text Immediate Blit Enable. This bit controls how the GMCH handles blits. This bit must be programmed for proper operation 1 = Enable Disable. Do NOT program to 0 5:3 ...
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... SDRAM width for Row 2, if populated) Datasheet 92–93h FFFFh Read/Write SCS2# SCS3# Buffer Buffer Strength Strength CKE0 Buffer Strength MD and DQM Buffer Description ® Intel 82810E (GMCH SMAA[7:4] Buffer SMAB[7:4] Buffer Strength Strength 2 1 Control Buffer Strength Strength ...
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... Intel 82810E (GMCH) Bit 12 SCS3# Buffer Strength. This field sets the buffer strength for system memory chip buffer SCS3 3x loads 2x loads) load = (64 / SDRAM width for Row 3, if populated) 11:10 SMAA[7:4] Buffer Strength. This field sets the buffer strength for SMAA[7:4] buffers. ...
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... Video Bios ROM Base Address Capabilities Pointer Reserved Interrupt Line Register Interrupt Pin Register Minimum Grant Register Maximum Latency Register Reserved Power Management Capabilities ID Power Management Capabilities Power Management Control Reserved ® Intel 82810E (GMCH) Default Value Access 8086h RO 7125h RO 0004h R/W 02B0h RO, R/WC 03h ...
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... The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect. Bit 15:0 Vendor Identification Number. This is a 16-bit value assigned to Intel. DID Device Identification Register (Device 1) 3.5.2. Address Offset: ...
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... Enable. Datasheet 04h−05h 0004h Read Only, Read/Write Reserved ( VGA Pal Mem WR Special Sn & Inval En Cycle En (Not Impl) (Not Impl) (Not Impl) Descriptions ® Intel 82810E (GMCH FB2B SERR En (Not Impl) (Not Impl Bus Mem Acc I/O Acc En Master En En (Enabled ...
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... Intel 82810E (GMCH) PCISTS PCI Status Register (Device 1) 3.5.4. Address Offset: Default Value: Access: PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the GMCH hardware ...
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... Sub-Class Code (SUBC). This is an 8-bit value that indicates the category of display controller of the GMCH. The code is 00h indicating a VGA compatible device. Datasheet 08h 03h Read Only Description 09h 00h Read Only Description 0Ah 00h Read Only 8 bits Description ® Intel 82810E (GMCH) 53 ...
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... Intel 82810E (GMCH) 3.5.8. BCC1—Base Class Code Register (Device 1) Address Offset: Default Value: Access: Size: This register contains the Base Class Code of the GMCH Function #1. Bit 7:0 Base Class Code (BASEC). This is an 8-bit value that indicates the Base Class Code for the GMCH. ...
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... This register is used for control and status of Built In Self Test (BIST) for the internal graphics device of the GMCH BIST Supported (HW=0) Bit 7 BIST Supported. BIST is not supported. This bit is hardwired to 0. 6:0 Reserved Datasheet 0Eh 00h Read Only Description 0Fh 00h Read Only Reserved Descriptions ® Intel 82810E (GMCH ...
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... Intel 82810E (GMCH) GMADR Graphics Memory Range Address Register (Device 1) 3.5.13. Address Offset: Default Value: Access: This register requests allocation for the internal graphics device of the GMCH local memory. The allocation is for either memory space (selected by bit 0 of the Device 0 MISCC Register) and the base address is defined by bits [31:25,24] ...
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... Read_Only. This Register can only be cleared by a Reset. Datasheet 14−17h 00000000h Read/Write, Read Only Memory Base Address (addr bits [31:19 Prefetch Mem En (HW=0) Descriptions 2C−2Dh 0000h Read/Write Once Descriptions ® Intel 82810E (GMCH Address Mask (HW=0; 512KB addr range Memory Type Mem/IO (HW=0; 32MB addr) Space (HW=0) 57 ...
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... Intel 82810E (GMCH) SID Subsystem Identification Register (Device 1) 3.5.16. Address Offset: Default Value: Access: Bit 15:0 Subsystem ID—R/WO. This value is used to identify a particular subsystem. The default value is 0000h. This field should be programmed by BIOS during boot-up. Once written, this register becomes Read_Only. This Register can only be cleared by a Reset. ROMADR ...
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... Maximum Latency Value. Bits[7:0]=00h. The GMCH has no specific requirements for how often it needs to access the PCI bus. Datasheet 3Ch 00h Read/Write Descriptions 3Dh 01h Read Only Descriptions 3Eh 00h Read Only Descriptions 3Fh 00h Read Only Descriptions ® Intel 82810E (GMCH) 59 ...
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... Intel 82810E (GMCH) PM_CAPID Power Management Capabilities ID Register 3.5.23. (Device 1) Address Offset: Default Value: Access: 15 Bits 15:8 NEXT_PTR. This contains a pointer to next item in capabilities list. This the final capability in the list and must be set to 00h. 7:0 CAP_ID. SIG defines this ID is 01h for power management. PM_CAP ...
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... GMCH into a new power state. If software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs Reserved 10 = Reserved Datasheet E0h−E1h 0000h Read/Write 13 12 Data_Select (Reserved) Reserved Description ® Intel 82810E (GMCH PME PowerState 61 ...
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... DRAM Populated (DP). The bit in this register indicates whether or not the Display Cache is populated Display Cache Display Cache 62 Register Register Name Symbol DRAM Row Type DRAM Control Low DRAM Control High Intel Reserved Intel Reserved Reserved 3000h 00h Read / write 8 bit Reserved Description R Default Value Access 00h ...
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... RAS# Precharge Timing (RPT). This bit controls RAS# precharge (in local memory clocks (default) Datasheet 3001h 17h Read / write 8 bit 5 4 Paging RAS-to- Mode Control Override Description RAS#-to-CAS# delay (t ) RCD (default) ) Refresh to RAS# act. (t RAS 5 7 ® Intel 82810E (GMCH CAS# RAS# CAS Latency Riming Precharge ) (default) 0 RAS# Timing 63 ...
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... Intel 82810E (GMCH) 3.6.3. DRAMCH—DRAM Control High Memory Offset Address: Default Value: Access: Size: 7 Reserved Bit 7:5 Reserved 4:3 DRAM Refresh Rate (DRR). DRAM refresh is controlled using this field. Disabling refresh results in the eventual loss of DRAM data, although refresh can be briefly disabled without data loss. The field must be set to normal refresh as soon as possible once DRAM testing is completed ...
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... MMADR register (Device 1, PCI configuration offset 14h). For each register, the memory-mapped address offset is the same address value as the I/O address. See ® the Intel 810E chipset BIOS specification for the proper setting of these registers for display cache detection and diagnostics. ...
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... Intel 82810E (GMCH) MSR Miscellaneous Output 3.7.2. I/O (and Memory Offset) Address: Default: Attributes: 7 Bit 7:2 Reserved A0000− − − − BFFFFh Access Enable. VGA Compatibility bit enables access to the display cache at 1 A0000h−BFFFFh. When disabled, accesses to system memory are blocked in this region (by not asserting DEVSEL#) ...
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... B0000h − B7FFFh 11 = B8000h − BFFFFh Note: This function is both in standard VGA modes and in extended modes that do not provide linear frame buffer accesses. 1:0 Reserved Datasheet 3CFh (Index=06h) 0Uh (U=Undefined) Read/Write 4 3 Reserved Memory Map Mode Description ® Intel 82810E (GMCH Reserved 67 ...
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... Intel 82810E (GMCH) GR10 Address Mapping 3.7.4. I/O (and Memory Offset) Address: Default: Attributes: 7 Reserved Bit 7:5 Reserved 4 Page to Display Cache Enable Page to VGA Buffer Page to Display Cache. 3 VGA Buffer/Memory Map Select VGA Buffer (default Memory Map. ...
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... NON-OVERLAPPING. There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges. Accesses to overlapped ranges may produce indeterminate results. Datasheet ® III processor, Intel Pentium II processor, or Intel Pentium II processor, and Intel ® Intel 82810E (GMCH) TM Celeron processor system ...
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... Intel 82810E (GMCH) 4.1.1. Memory Address Ranges Figure 3 shows a high-level representation of the system memory address map. Figure 4 provides additional details on mapping specific memory regions as defined and supported by the GMCH chipset. Figure 3. System Memory Address Map Top of the Main Memory PCI ...
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... Device Memory 16 MB Optional ISA Hole Video BIOS DOS (shadowed in memory) Compatibility Graphics Adapter Memory (128 KB) System/Application SW ® Intel 82810E (GMCH) 0FFFFFh Segment F (BIOS Shadow Area, etc.) 0F0000h 0EFFFFh Main Segment E (BIOS Shadow Area, etc.) 0E0000h 0DFFFFh Optional CD Hole 0DC000h 0DBFFFh Segment D (BIOS Shadow Area, etc ...
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... Intel 82810E (GMCH) Table 7 lists the memory segments of interest in the compatibility area. Four of the memory ranges can be enabled or disabled independently for both read and write cycles. One segment (0DC000h to 0DFFFFh) is conditionally mapped to the PCI Bus (via the hub interface). Table 7. Memory Segments and their Attributes Memory Segments 000000h– ...
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... Plug and Play. The base address is programmed in the MMADR PCI Configuration Register for Device 1. Note that, for legacy support, the VGA registers in the GMCH’s graphics controller are also mapped to the normal I/O locations. Datasheet ® Intel 82810E (GMCH) 73 ...
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... Memory Space Map (512 KB allocation) Intel Reserved Intel Reserved Intel Reserved Intel Reserved Intel Reserved Intel Reserved Intel Reserved Intel Reserved Intel Reserved Display Cache Interface Control Registers I/O Space Map Intel Reserved (Standard graphics locations) VGA and Ext. VGA Registers VGA and Ext ...
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... Optional larger write-back cacheable T_SEG area of either 512 KB or 1MB in size above 1 MB that is reserved from the highest area in system DRAM memory. The above 1 MB solutions require changes to compatible SMRAM handlers code to properly execute above 1 MB. Refer to the Power Management section for more details on SMRAM support. Datasheet ® Intel 82810E (GMCH) 75 ...
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... Intel 82810E (GMCH) 4.1.2. Memory Shadowing Any block of memory that can be designated as read-only or write-only can be “shadowed” into the GMCH DRAM memory. Typically this is done to allow ROM code to execute more rapidly out of main DRAM. ROM is used as a read-only during the copy process while DRAM at the same time is designated write-only ...
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... SC242 processor connectors. 4.2.1. Host Bus Device Support The GMCH recognizes and supports a large subset of the transaction types that are defined for the Intel Pentium III processor, Intel However, each of these transaction types have a multitude of response types, some of which are not supported by this controller ...
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... Intel 82810E (GMCH) Table 8. Summay of Transactions Supported By GMCH Transaction Deferred Reply Reserved Interrupt Acknowledge Special Transactions Reserved Reserved Branch Trace Message Reserved Reserved Reserved I/O Read I/O Write Reserved Memory Read & Invalidate Reserved Memory Code Read Memory Data Read ...
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... Implicit This response is given for those transactions where the Writeback initial transactions snoop hits on a modified cache line. 1 Normal Data This response is for transactions where data accompanies Response the response phase. Reads receive this response. ® Intel 82810E (GMCH) GMCH Support 79 ...
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... Intel 82810E (GMCH) 4.2.2. Special Cycles A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. The first address phase Aa[35:3]# is undefined and can be driven to any value. The second address phase, Ab[15:8]# defines the type of Special Cycle issued by the processor. Table 10 specifies the cycle type and definition as well as the action taken by the GMCH when the corresponding cycles are identified ...
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... SDRAMs. Table 11 illustrates a sample of the possible DIMM socket configurations along with corresponding DRP programming. See the register section of this document for a complete DRP programming table. Datasheet SMD[63:0] SDQM[7:0] SMAA[11:8,3:0] SBS[1:0] SCS[3:0]# SCAS# SRAS# SWE# SCKE[1:0] ® Intel 82810E (GMCH) 81 ...
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... BIOS essentially needs to determine the size and type of memory used for each of the four rows of memory in order to properly configure the GMCH system memory interface. SMBus Configuration and Access of the Serial Presence Detect Ports For more details on this see the Intel datasheet. 4.3.1.2. ...
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... These addresses are derived from the host address bus as defined by by the following table for SDRAM devices. Row size is internally computed using the values programmed in the DRP register pages can be open at any time within any row (Only 2 active pages are supported in rows populated with either 8 MBs or 16 MBs ). Datasheet ® Intel 82810E (GMCH) Function 83 ...
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... Intel 82810E (GMCH) Table 13. GMCH DRAM Address Mux Function Tech Depth Wid 16Mb 1MB 16 16Mb 2MB 64Mb 2MB 32 64Mb 4MB 16 64Mb 8MB 128Mb 4MB 32 128Mb 8MB 16 128Mb 16MB NOTES: 1. [A]; MA bit 10 at RAS time uses the XOR of Address bit 12 and Address bit 23 ...
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... GMCH can support any combination of CAS# Latency, RAS# to CAS# Delay and RAS# Precharge. Datasheet SCKE0 SCKE1 SRAS# SCAS# SWE# DRAMT Bit ® Intel 82810E (GMCH) Note: - Min (16Mbit Max (64Mbit) 256 MB - Max (128Mbit) 512 MB mem_dimm Values (SCLKs) 2,3 2,3 2,3 Tras = 5,6 Trc = 7,8 ...
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... Dynamic Video Memory Technology (D.V.M.T.) The internal graphics device on the 810E supports Intel (D.V.M.T.). D.V.M.T. dynamically responds to application requirements by allocating the proper amount of display and texturing memory. For more details, refer to the document entitled, “Intel Chipset: Great Performance for Value PCs” available at: http://developer.intel.com/design/chipsets/810/810white.htm. ...
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... Density 16 Mbit 1M Figure 7 shows the GMCH LMI connected memory in a 32-bit SDRAM channel configuration. Figure 7. GMCH Display Cache Interface Datasheet SDRAM # of Address Size Width Banks Bank Row Column GMCH ( SDRAM ® Intel 82810E (GMCH) DRAM DRAM Size Addressing Asymmetric 4MB Dply_C_inter 87 ...
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... Intel 82810E (GMCH) 4.5.3. Address Translation The GMCH contains address decoders that translate the address received by the display cache into an effective display cache address. The LMA[11:0] bits are as defined below. Entries in the table (e.g., A21(X)) imply that the GMCH puts out A21 on that MA line but it is not used by the SDRAM. ...
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... Instruction Batch Buff Instr Instruction access and decoding DMA Instruction DMA FIFO Interrupt Ring (Graphics Memory) Instruction DMA Batch Buff Instr Instruction ® Intel 82810E (GMCH) 2D Instructions BLT Engine Instr Parser 3D Instructions (3D state, 3D Primitives, STRBLT, Motion Compensation) 3D Engine Display Engine Overlay Engine cmd_str ...
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... Intel 82810E (GMCH) 4.6.2. 3D Engine The 3D engine of the GMCH has been architected as a deep pipeline, where performance is maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or portions of the same primitive. The internal graphics device of the GMCH supports perspective-correct texture mapping, bilinear and anisotropic MIP mapping, gouraud shading, alpha-blending, fogging and Z Buffering ...
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... Back Face Culling”). Datasheet GMCH Graphics Pipeline (Conceptual Representation) Setup Mapping Engine Color Calculator GMCH Interface ® Intel 82810E (GMCH) Discard (Back Face Culling) Primitives Pixels Rasterize 3d_pipe2 91 ...
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... Intel 82810E (GMCH) 4.6.5. Texturing The internal graphics device of the GMCH allows an image, pattern, or video to be placed on the surface polygon. Textures must be located in system memory. Being able to use textures directly from system memory means that large complex textures can easily be handled without the limitations imposed by the traditional approach of only using the display cache ...
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... Supporting these techniques in hardware greatly increases compositing performance by reducing the need to read and write the frame buffer multiple times. Datasheet ® Intel 82810E (GMCH) 93 ...
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... The 2D registers are a combination of registers defined by IBM* when the Video Graphics Array (VGA) was first introduced, and others that Intel has added to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard. The internal graphics device of the GMCH improves upon VGA by providing additional features that are used through numerous additional registers ...
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... DVD implementations), the 82810E graphics device supports downsampled MPEG decoding. Downsampling allows for reduced spatial resolution in the MPEG picture while maintaining a full frame rate, and thus reduces processor load while maintaining the best video quality possible given the processor constraints. Datasheet ® Intel 82810E (GMCH) 95 ...
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... Intel 82810E (GMCH) 4.6.9. Hardware Cursor The internal graphics device of the GMCH allows unlimited number of cursor patterns to be stored in the display cache or system memory. Two sets of registers, contain the x and y position of the cursor relative to the upper left corner of the display. The following four cursor modes are provided: • ...
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... Bits Per Pixel (frequency in Hz) 8-bit Indexed 16-bit 60,70,72,75,85 60,70,72,75,85 75,85 75,85 60,75,85 60,75,85 60,70,72,75,85 60,70,72,75,85 60, 70,72,75,85 60, 70,72,75,85 60,70,72,75,85 60,70,72,75,85 60,75,85 60,75,85 60,75,85 60,75,85 60,70,72,75,85 60,70,72,75,85 60,75,85 60,75,85 60,70,72,75,85 ® Intel 82810E (GMCH) 24-bit 60,70,72,75,85 75,85 60,75,85 60,70,72,75,85 60, 70,72,75,85 60,70,72,75,85 60,75,85 60,75,85 60,70,75,85 97 ...
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... Intel 82810E (GMCH) Table 17. Overlay Modes Supported Pixel Resolution 640x480 720x480 720x576 800x600 1024x768 1152x864 1280x1024 1600x1200 NOTES: 1. Overlay support modified in the 2.2 driver Available Desktop Mode Overlay Support 98 Colors 60Hz 70Hz 256 D/Y D/Y 16 Bit D/Y D/Y 24 Bit D/Y ...
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... Connecting the GMCH to a flat panel transmitter is demonstrated below. For more details, refer to the ® Intel 810E Chipset Design Guide at http://developer.intel.com/design/chipsets/designex/290675.htm. The GMCH supports a variety of Flat Panel display modes and refresh rates that require MHz dot clock over this interface. Table 18 shows some of the display modes supported by the GMCH. Table 19 shows some of the TV-Out modes supported by the GMCH ...
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... Intel 82810E (GMCH) Table 19. Partial List of TV-Out Modes Supported Resolution 1 320x200 320x240 1 352x480 1 352x576 1 400x300 1 640x400 640x480 1 720x480 1 720x576 800x600 NOTES: 1. These resolutions are supported via centering. 4.6.13. DDC (Display Data Channel) DDC is a standard defined by VESA. Its purpose is to allow communication between the host system and display ...
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... Chipset Design Guide (Power Sequencing section) for details. 4.8. System Clock Description The 810E Chipset is supported by a CK810E clock synthesizer. Refer to the Intel Guide for details. CK810E Features (56 Pin SSOP Package): • 3 copies of processor Clock 66/100/133 MHz (2.5V) [processor, GCH, ITP] • ...
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... Intel 82810E (GMCH) 4.9.2. ACPI Rev 1.0 — Support for Resume From S3 State The 82810E enters self-refresh upon entering S3 (Suspend to RAM). The normal sequence is that the GMCH sends a “Precharge All banks” to SDRAM and then issues an “Enter Self-Refresh” command prior to actually entering the S3 state. However, the GMCH may issue an " ...
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... R 5. Pinout and Package Information 5.1. 82810E GMCH Pinout Figure 10 and Figure 11 show the ball foot print of the 82810E. These figures represent the ballout by ball number. Table 19 provides an alphabetical signal listing of the ballout. Datasheet ® Intel 82810E (GMCH) 103 ...
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... Intel 82810E (GMCH) Figure 10. GMCH Pinout (Top View—Left Side VSS SCKE1 B SDQM2 VSUS_3.3 C SDQM6 SCS3# D SDQM3 SDQM7 E SMD16 VSS F SMD49 SMD17 G SMD19 SMD50 H SMD22 SMD21 J SMD24 VSS K SMD26 SMD25 L SMD28 SMD29 M VSS RESET# N DRDY# RS2# P HIT# RS1# R HITM# HREQ3# ...
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... HD52# HD57# HD54# HD56# DDCSDA HD47# HD59# HD46# HD61# HD40# VSS HD55# HD50# HD51# HD27# HD63# HD53# HD41# HD49# HD48# HD62# ® Intel 82810E (GMCH HL10 HLSTRB# HLSTRB HL8 HL4 V_1.8 VSS HL2 VSS HL9 HL0 LMD23 HLCLK HUBREF LMD22 LMD20 ...
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... Intel 82810E (GMCH) Table 20. Alphabetical Pin Assignment Pin Name Ball # ADS# N3 BLANK# V19 BLUE AC23 BNR# T3 BPRI# T1 CLKOUT0 V21 CLKOUT1 V22 CPURST# AB4 DBSY# M4 DCLKREF AA21 DDCSCL W20 DDCSDA W19 DEFER# R3 DRDY# N1 GREEN AC22 GTLREFA M5 GTLREFB W13 HA3# U5 HA4# U1 HA5# ...
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... SMAA8 LTVDATA9 T23 SMAA9 LTVDATA10 T22 SMAA10 LTVDATA11 T21 SMAA11 LWE# J19 SMAB4# RED AC21 SMAB5# RESET# M2 SMAB6# RS0# N5 SMAB7# RS1# P2 ® Intel 82810E (GMCH) Ball # Pin Name RS2# N2 SMD1 SBS0 C5 SMD2 SBS1 E5 SMD3 A11 SMD4 A3 SMD5 A2 SMD6 SCLK E6 SMD7 C4 SMD8 C3 ...
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... Intel 82810E (GMCH) Pin Name Ball # SMD37 E12 SMD38 D12 SMD39 B15 SMD40 B12 SMD41 C12 SMD42 D11 SMD43 D10 SMD44 E10 SMD45 E9 SMD46 E8 SMD47 C8 SMD48 F3 SMD49 F1 SMD50 G2 SMD51 H3 SMD52 E4 SMD53 E3 SMD54 F4 SMD55 J3 SMD56 F5 SMD57 G5 SMD58 H5 SMD59 H4 SMD60 H6 SMD61 J5 SMD62 ...
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Package Dimensions This section shows the mechanical dimensions for the 82810E. The package is a 421 Ball Grid Array (BGA). Figure 12. GMCH Package Dimensions (421 BGA) – Top and Side Views Pin A1 corner Pin A1 I.D. 45° ...
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... Intel 82810E (GMCH) Figure 13. GMCH Package Dimensions (421 BGA) – Bottom View Table 21. GMCH Package Dimensions (421 BGA) Symbol 30.80 D1 25.80 E 30.90 E1 25. NOTES: Notes: 1. All dimensions and tolerances conform to ANSI Y14.5-1982 2. Dimension is measured at maximum solder ball diameter parallel to primary datum (-C-) 3 ...
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... Deassert RESET# high and LMD30 high 2. Assert RESET# low; maintain LMD30 high 3. Deassert RESET# high; maintain LMD30 high 4. RESET# must be maintained high for the duration of testing. No external clocking of the GMCH is required. Datasheet Pin 3 Pin 4 ® Intel 82810E (GMCH) XOR Out Pin 5 Pin 6 xor.vsd 111 ...
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... Intel 82810E (GMCH) 6.1. XOR TREE Testability Algorithm Example XOR tree testing allows users to check, for example, opens and shorts to VCC or GND. An example algorithm to do this is shown in Table 22. Table 22. XOR Test Pattern Example Vector PIN1 this example, Vector 1 applies all “0s” to the chain inputs. The outputs being non-inverting, will consistently produce a “ ...
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... Assert RESET# low for 35,000 HLCLKs; maintain LMD31 high 4. Deassert RESET# high for 35,000 HLCLKs; maintain LMD31 high 5. Chain #3 is now initialized and ready to begin XOR test. RESET# must be maintained high for the duration of testing. Datasheet ® Intel 82810E (GMCH) 113 ...
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... Intel 82810E (GMCH) 6.3. XOR Chain Pin Assignment Table 23. XOR Chain 1 Pin Name Ball# LMD6 (start) R19 LMD7 R20 LMD9 R21 LMD8 R22 LMA1 P19 LDQM1 R23 LMA2 P20 LDQM0 P21 LMD11 P22 LMD10 P23 LMA3 N19 LMD14 N20 LMD13 ...
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... NOTES: 1. Chain 3 = Even Number of XOR Gates: All “1s” yields 1.5V LTVDATA0 = “1” 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V ® Intel 82810E (GMCH) Ball# Voltage Y14 1.5V AC15 1.5V AB15 1.5V AA15 1.5V Y15 1.5V AC16 1.5V W15 1 ...
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... Intel 82810E (GMCH) Table 26. XOR Chain 4 Pin Name Ball# HD27# (start) AB16 HA14# T5 HA16# V2 HA11# U4 HA10# W1 HA3# U5 HA15# W2 HA28# Y1 HA5# V4 HA12# W3 HA25# Y2 HA21# AA1 HD8# V5 HA13# W4 HA19# Y3 HA18# AA2 HA31# AB1 HA24# AA3 HA22# AB2 HD1# W5 HA30# Y4 HA17# AC2 HA20# ...
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... Chain 5 Output 3.3V SMAA0 3.3V NOTES: 1. Chain 5 = Odd Number of XOR Gates: All “1s” yields 3.3V SMAA0 = “0” 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 1.5V 1.5V 1.5V ® Intel 82810E (GMCH) Ball# Voltage N3 1.5V N4 1.5V N5 1.5V P1 1.5V P2 1.5V P4 1. ...
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... Intel 82810E (GMCH) Table 28. XOR Chain 6 Pin Name Ball# HLSTRB#(start) A20 SMD8 A15 SMD34 D14 SMD9 C14 SMD10 B14 SMD11 A14 SMD36 E13 SMD12 D13 SMD13 C13 SMD14 A13 SMD37 E12 SMD38 D12 SMD41 C12 SMD40 B12 SMD15 A12 ...
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... SMD35 1.8V length=25 1.8V Chain 7 Output 1.8V SWE# 3.3V NOTES: 1. Chain 7 = Odd Number of XOR Gates: All “1s” yields 3.3V SWE# = “1” ® Intel 82810E (GMCH) Ball# Voltage C17 3.3V D16 3.3V A17 3.3V C16 3.3V E15 3.3V B16 3 ...