NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 14

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
1.3.
1.4.
1.5.
1.6.
14
®
82810E (GMCH)
Host Interface
The host interface of the GMCH is optimized to support the Intel
Intel
control, and data bus interfaces within a single device. The GMCH supports a 4-deep in-order queue
(i.e., supports pipelining of up to 4 outstanding transaction requests on the host bus) . Host bus addresses
are decoded by the GMCH for accesses to system memory, PCI memory and PCI I/O (via hub interface),
PCI configuration space and Graphics memory. The GMCH takes advantage of the pipelined addressing
capability of the processor to improve the overall system performance.
The GMCH supports the 370-pin socket and SC242 processor connectors.
System Memory Interface
The GMCH integrates a system memory DRAM controller that supports a 64-bit 100 MHz DRAM array.
The DRAM type supported is industry standard Synchronous DRAM (SDRAM). The DRAM controller
interface is fully configurable through a set of control registers. Complete descriptions of these registers
are given in the Chapter 3, “Configuration Registers”.
The GMCH supports industry standard 64-bit wide DIMM modules with SDRAM devices. The twelve
multiplexed address lines, SMAA[11:0], along with the two bank select lines, SBS[1:0], allow the
GMCH to support 2M, 4M, 8M, and 16M x64 DIMMs. Only asymmetric addressing is supported. The
GMCH has four SCS# lines, enabling the support of up to four 64-bit rows of DRAM. The GMCH
targets SDRAM with CL2 and CL3 and supports both single and double-sided DIMMs. Additionally, the
GMCH also provides a seven deep refresh queue. The GMCH can be configured to keep multiple pages
open within the memory array, pages can be kept open in any one row of memory.
SCKE[1:0] is used in configurations requiring powerdown mode for the SDRAM.
Display Cache Interface
The 82810E GMCH supports a Display Cache DRAM controller with a 32-bit 100/133 MHz DRAM
array. The DRAM type supported is industry standard Synchronous DRAM (SDRAM) like that of the
system memory. The local memory DRAM controller interface is fully configurable through a set of
control registers. Complete descriptions of these registers are given in Chapter 3, “Configuration
Registers”.
Hub Interface
The hub interface is a private interconnect between the GMCH and the ICH.
• 370-pin socket (PGA370). The zero insertion force (ZIF) socket that a processor in the PPGA
• SC242—242-contact slot connector. A processor in a Single-Edge Processor Package (SEPP) or

package will use to interface with a system board.
Single-Edge Contact Cartidge (SECC and SECC2) use this connector to interface with a system
board.
Pentium
®
II processor, and Intel

Celeron
TM
processor. The GMCH implements the host address,

Pentium
®
III processor,
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