NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 85

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

4.3.3.
4.3.4.
Datasheet
Figure 6. DRAM Array Sockets (2 DIMM Sockets)
Table 14. Programmable SDRAM Timing Parameters
R
DRAM Array Connectivity
SDRAMT Register Programming
Several DRAM timing parameters are programmable in the GMCH configuration registers. Table 14
summarizes the programmable parameters.
These parameters are controlled via the DRAMT register. In order to support different device speed
grades, CAS# Latency, RAS# to CAS# Delay, and RAS# Precharge are all programmable as either two
or three SCLKs. To provide flexibility, these are each controlled by separate register bits. That is, the
GMCH can support any combination of CAS# Latency, RAS# to CAS# Delay and RAS# Precharge.
RAS# Precharge (SRP)
RAS# to CAS# Delay (SRCD)
CAS# Latency (CL)
DRAM Cycle Time (DCT)
DIMM_CLK[3:0]
DIMM_CLK[7:4]
SMAA[11:8,3:0]
Parameter
SMB_DATA
SMAB[7:4]#
SDQM[7:0]
SMAA[7:4]
SMD[63:0]
SMB_CLK
SCS[3:2]#
SCS[1:0]#
SBS[1:0]
SCKE0
SCKE1
SRAS#
SCAS#
SWE#
DRAMT Bit
0
1
2
4
Values (SCLKs)
Tras = 5,6
Trc = 7,8
Note:
- Min (16Mbit) 8 MB
- Max (64Mbit) 256 MB
- Max (128Mbit) 512 MB
2,3
2,3
2,3
Intel
®
82810E (GMCH)
mem_dimm
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