NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 46

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
3.4.20.
46
®
82810E (GMCH)
MISCC2    Miscellaneous Control 2 Register (Device 0)
Address Offset:
Default Value:
Access:
This register controls miscellaneous functionality in the GMCH.
Bit
5:3
(must be 1)
7
6
2
1
0
Reserved
Intel
7
Intel Reserved. This Bit must be programmed to 1.
Do not program to 0.
Text Immediate Blit Enable. This bit controls how the GMCH handles blits. This bit must be
programmed to a 1 for proper operation
1 = Enable.
0 = Disable. Do NOT program to 0
Reserved
Palette Load Select. This bit controls how the palette is loaded in the GMCH. This bit must be
programmed to 1 for proper operation.
1 = Enable.
0 = Disable. Do NOT program to 0.
Instruction Parser Unit-Level Clock Gating Enable. This bit controls the unit-level clock gating in the
Instruction Parser. This bit must be programmed to 1 for proper operation.
1= Enable.
0 = Disable. Do NOT program to 0.
Reserved
Blit Enable
Immediate
Text
6
5
80h
00h
Read/Write
Reserved
Description
3
Palette
Select
Load
2
Unit-Lrvel
Enable
Parser
Clock
Instr.
1
Reserved
Datasheet
Intel
0
R