NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 27

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.2.2.
3.2.3.
3.2.4.
3.2.5.
Datasheet
R
Logical PCI Bus #0 Configuration Mechanism
Primary PCI (PCI0) and Downstream Configuration Mechanism
Internal Graphics Device Configuration Mechanism
GMCH Register Introduction
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration
cycle is targeting a PCI Bus #0 device.
If the Bus Number in the CONFIG_ADDRESS register is non-zero the GMCH will generate a
configuration cycle over the hub interface. The ICH compares the non-zero Bus Number with the
Secondary Bus Number and Subordinate Bus Number registers of its P2P bridges to determine if the
configuration cycle is meant for Primary PCI (PCI0), or a downstream PCI bus.
From the chipset configuration perspective the internal graphics device is seen as a PCI device
(device #1) on PCI Bus #0. Configuration cycles that target device #1 on PCI Bus #0 are claimed by the
internal graphics device and are not forwarded via hub interface to the ICH.
The GMCH contains two sets of software accessible registers, accessed via the Host I/O address space:
The GMCH supports PCI configuration space accesses using the mechanism denoted as Configuration
Mechanism #1 in the PCI specification.
The GMCH internal registers (both I/O Mapped and Configuration registers) are accessible by the host.
The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of
CONFIG_ADDRESS register that can only be accessed as a DWord. All multi-byte numeric fields use
"little-endian" ordering (i.e., lower addresses contain the least significant parts of the field).
• Device #0: The Host-hub interface Bridge/DRAM Controller entity within the GMCH is hardwired
•
• Control registers I/O mapped into the host I/O space, that control access to PCI configuration space
• Internal configuration registers residing within the GMCH are partitioned into two logical device
as Device #0 on PCI Bus #0.
Device #1: The internal graphics device entity within the GMCH is hardwired as Device #1 on PCI
Bus #0. Configuration cycles to one of the GMCH internal devices are confined to the GMCH and
not sent over the hub interface. Note: Accesses to devices #2 to #31 on PCI Bus #0 will be
forwarded over the hub interface.
(see section entitled I/O Mapped Registers)
register sets (“logical” since they reside within a single physical device). The first register set is
dedicated to Host-hub interface Bridge/DRAM Controller functionality (controls PCI0 such as
DRAM configuration, other chip-set operating parameters and optional features). The second
register block is dedicated to the internal graphics device in the GMCH.
Intel
®
82810E (GMCH)
27