NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 21

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

2.5.
Datasheet
R
Display Interface Signals
VSYNC
HSYNC
IWASTE
IREF
RED
GREEN
BLUE
DDCSCL
DDCSDA
Signal Name
O
3.3V
O
3.3V
I
Ref
I
Ref
O
Analog
O
Analog
O
Analog
I/OD
CMOS
I/OD
CMOS
Type
CRT Vertical Synchronization: This signal is used as the vertical sync (polarity is
programmable) or “ Vsync Interval”.
CRT Horizontal Synchronization: This signal is used as the horizontal sync
(polarity is programmable) or “ Hsync Interval”.
Waste Reference: This signal must be tied to ground.
Set pointer resistor for the internal color palette DAC: A 174 ohm 1% resistor is
recommended
CRT Analog video output from the internal color palette DAC: The DAC is
designed for a 37.5 ohm equivalent load on each pin (e.g. 75 ohm resistor on the
board, in parallel with the 75 ohm CRT load)
CRT Analog video output from the internal color palette DAC: The DAC is
designed for a 37.5 ohm equivalent load on each pin (e.g., 75 ohm resistor on the
board, in parallel with the 75 ohm CRT load)
CRT Analog video output from the internal color palette DAC: The DAC is
designed for a 37.5 ohm equivalent load on each pin (e.g., 75 ohm resistor on the
board, in parallel with the 75 ohm CRT load)
CRT Monitor DDC Interface Clock: (Also referred to as VESA
Channel”, also referred to as the “Monitor Plug-n-Play” interface.) For DDC1,
DDCSCL and DDCSDA provides a unidirectional channel for Extended Display ID.
For DDC2, DDCSCL and DDCSDA it can be used to establish a bi-directional
channel based on I
Display Interface information over the DDC2 channel.
CRT Monitor DDC Interface Data:
2
C protocol. The host can request Extended Display ID or Video
Description
Intel
®
TM
82810E (GMCH)
“Display Data
21