NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 25

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.
3.1.
Datasheet
R
Configuration Registers
This section describes the following register sets:
Note that the GMCH also contains an extensive set of registers and instructions for controlling its
graphics operations. Intel graphics drivers provide the software interface at this architectural level. The
register/instruction interface is transparent at the Application Programmers Interface (API) level and
thus, beyond the scope of this document.
Register Nomenclature and Access Attributes
RO
R/W
R/WC
R/WO
Reserved
Bits
Reserved
Registers
Default
Value
Upon
Reset
• PCI Configuration Registers . The GMCH contains PCI configuration registers for Device 0 (Host-
• Display Cache Interface Registers. This register set is used for configuration of the Display Cache
• Display Cache Detect and Diagnostic Registers. This register set can be used for DC memory
hub interface Bridge/DRAM Controller) and Device 1 (GMCH internal graphics device).
(DC) interface. The registers are located in memory space. The memory space addresses listed are
offsets from the base memory address programmed into the MMADR register (Device 1, PCI
configuration offset 14h).
detection and testing. These registers are accessed via either I/O space or memory space. The
memory space addresses listed are offsets from the base memory address programmed into the
MMADR register (Device 1, PCI configuration offset 14h).
Read Only. If a register is read only, writes to this register have no effect.
Read/Write. A register with this attribute can be read and written
Read/Write Clear. A register bit with this attribute can be read and written. However, a write of a 1
clears (sets to 0) the corresponding bit and a write of a 0 has no effect.
Read/Write Once. A register bit with this attribute can be written to only once after power up. After
the first write, the bit becomes read only.
Some of the GMCH registers described in this section contain reserved bits. These bits are labeled
"Reserved” or “Intel Reserved”. Software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined bits and not rely on reserved
bits being any particular value. On writes, software must ensure that the values of reserved bit
positions are preserved. That is, the values of reserved bit positions must first be read, merged
with the new values for other bit positions and then written back. Note the software does not need
to perform read, merge, write operation for the configuration address register.
In addition to reserved bits within a register, the GMCH contains address locations in the
configuration space of the Host-hub interface Bridge/DRAM Controller and the internal graphics
device entities that are marked either "Reserved” or Intel Reserved”. When a “Reserved” register
location is read, a random value can be returned. (“Reserved” registers can be 8-, 16-, or 32-bit in
size). Registers that are marked as “Reserved” must not be modified by system software. Writes to
“Reserved” registers may cause system failure.
Upon a Full Reset, the GMCH sets all of its internal configuration registers to predetermined
default states. Some register values at reset are determined by external strapping options. The
default state represents the minimum functionality feature set required to successfully bring up the
system. Hence, it does not represent the optimal system configuration. It is the responsibility of the
system initialization software (usually BIOS) to properly determine the DRAM configurations,
operating parameters and optional system features that are applicable, and to program the GMCH
registers accordingly.
Intel
®
82810E (GMCH)
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