NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 63

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.6.2.
Datasheet
R
DRAMCL—DRAM Control Low
Memory Offset Address:
Default Value:
Access:
Size :
7:5
Bit
7
4
3
2
1
0
Reserved
Paging Mode Control (PMC).
0 = Page Open Mode. In this mode the GMCH memory controller tends to leave pages open.
1 = Page Close Mode. In this mode the GMCH memory controller tends to leave pages closed.
RAS-to-CAS Override (RCO). In units of display cache clock periods indicates the RAS#-to-CAS# delay
(t
0 = Determined by CL bit (default)
1 = 2
CAS# Latency (CL). In units of local memory clock periods.
Bit
0
1
RAS# Timing (RT). This bit controls RAS# active to precharge, and refresh to RAS# active delay (in
local memory clocks).
Bit RAS# act. To precharge (t
0
1
RAS# Precharge Timing (RPT). This bit controls RAS# precharge (in local memory clocks).
0 = 2
1 = 3 (default)
RCD
). (i.e., row activate command to read/write command)
CL
Reserved
2
3
RAS#-to-CAS# delay (t
5
7
2
3 (default)
5
3001h
17h
Read / write
8 bit
RAS
)
Control
Paging
Mode
RCD
Refresh to RAS# act. (t
4
)
Description
Override
RAS-to-
CAS
10 (default)
3
8
RC
Latency
)
CAS#
2
Intel
Riming
RAS#
1
®
82810E (GMCH)
Precharge
Timing
RAS#
0
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