NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 78

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
78
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Table 8. Summay of Transactions Supported By GMCH
82810E (GMCH)
NOTES:
Deferred Reply
Reserved
Interrupt
Acknowledge
Special
Transactions
Reserved
Reserved
Branch Trace
Message
Reserved
Reserved
Reserved
I/O Read
I/O Write
Reserved
Memory Read &
Invalidate
Reserved
Memory Code
Read
Memory Data
Read
Memory Write
(no retry)
Memory Write
(can be retried)
1. For Memory cycles, REQa[4:3]# = ASZ#. GMCH only supports ASZ# = 00 (32 bit address).
2. REQb[4:3]# = DSZ#. DSZ# = 00 (64 bit data bus size).
3. LEN# = data transfer length as follows:
Transaction
LEN#
00
01
10
11
0 0 0 0 0
0 0 0 0 1
0 1 0 0 0
0 1 0 0 0
0 1 0 0 0
0 1 0 0 0
0 1 0 0 1
0 1 0 0 1
0 1 0 0 1
0 1 0 0 1
1 0 0 0 0
1 0 0 0 1
1 1 0 0 x
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 0 1 0 1
0 0 1 1 1
Data length
<= 8 bytes (BE[7:0]# specify granularity)
Length = 16 bytes BE[7:0]# all active
Length = 32 bytes BE[7:0]# all active
Reserved
REQa[4:0]#
X X X X X
X X X X X
0 0 0 0 0
0 0 0 1 x
0 0 1 x x
0 0 0 0 0
0 0 0 0 1
0 0 0 1 x
0 0 1 x x
0 0 x LEN#
0 0 x LEN#
0 0 x x x
0 0 x LEN#
0 0 x LEN#
0 0 x LEN#
0 0 x LEN#
0 0 x LEN#
0 0 x LEN#
0 0 0 0 1
REQb[4:0]#
The GMCH initiates a deferred reply for a previously
deferred transaction.
Reserved
Interrupt acknowledge cycles are forwarded to the hub
interface.
See separate table in special cycles section.
Reserved
Reserved
The GMCH terminates a branch trace message without
latching data.
Reserved
Reserved
Reserved
I/O read cycles are forwarded to hub interface. I/O cycles
that are in the GMCH configuration space are not
forwarded to the hub interface.
I/O write cycles are forwarded to hub interface. I/O cycles
that are in the GMCH configuration space are not
forwarded to hub interface.
Reserved
Host initiated memory read cycles are forwarded to DRAM
or the hub interface.
Reserved
Memory code read cycles are forwarded to DRAM or hub
interface.
Host initiated memory read cycles are forwarded to DRAM
or the hub interface.
This memory write is a writeback cycle and cannot be
retried. The GMCH forwards the write to DRAM.
The standard memory write cycle is forwarded to DRAM or
hub interface.
GMCH Support
Datasheet
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