NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 86

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
4.3.5.
4.4.
4.5.
86
®
82810E (GMCH)
SDRAM Paging Policy
The GMCH can maintain up to 4 active pages in any one row; however, the GMCH does not support
active pages in more than 1 row at a time.
The DRAM page closing policy (DPCP) in the GMCH configuration register (GMCHCFG) controls the
page closing policy of the GMCH. This bit controls whether the GMCH precharges bank or precharge all
during the service of a page miss. When this bit is 0, the GMCH prechanges bank during the service of a
page miss. When this bit is 1, the GMCH prechanges all during the service of a page miss.
Intel
The internal graphics device on the 810E supports Intel
(D.V.M.T.). D.V.M.T. dynamically responds to application requirements by allocating the proper
amount of display and texturing memory. For more details, refer to the document entitled, “Intel
Chipset: Great Performance for Value PCs” available at:
In addition to D.V.M.T., the 82810E supports Display Cache (DC). The graphics engine of the 82810E
uses DC for implementing rendering buffers (e.g., Z buffers). This rendering model requires 4 MB of
display cache and allows graphics rendering (performed across the graphics display cache bus) and
texture MIP map access (performed across the system memory bus) simultaneously. Using D.V.M.T. all
graphics rendering is implemented in system memory. The system memory bus is arbitrated between
texture MIP-map accesses and rendering functions.
Display Cache Interface
The GMCH Display Cache (DC) is a single channel 32 bit wide SDRAM interface. The DC handles the
control and timing for the display cache. The display cache interface of the GMCH generates the LCS#,
LDQM[7:0], LSCAS#, LSRAS#, LWE#, LMD[31:0] and multiplexed addresses, LMA[11:0] for the
display cache DRAM array. The GMCH also generates the clock LTCLK for write cycles as well as
LOCLK for read cycle timings.
The display cache interface of the GMCH supports single data rate synchronous dynamic random access
memory (SDRAM). It supports a single 32-bit wide memory channel. The interface handles the operation
of D.V.M. with DC at 100/133 MHz. The DRAM controller interface is fully configurable through a set
of control registers.
Internal buffering (FIFOs) of the data to and from the display cache ensures the synchronization of the
data to the internal pipelines. The D.V.M. with DC interface clocking is divided synchronous with
respect to the core and system bus
http://developer.intel.com/design/chipsets/810/810white.htm.
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Dynamic Video Memory Technology (D.V.M.T.)
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Dynamic Video Memory Technology
Datasheet
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810
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