NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 94

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NH82810 S L7XK

Manufacturer Part Number
NH82810 S L7XK
Description
Manufacturer
Intel
Datasheet

Specifications of NH82810 S L7XK

Lead Free Status / RoHS Status
Compliant
Intel
4.6.6.
4.6.7.
94
®
82810E (GMCH)
2D Operation
Fixed Blitter (BLT) and Stretch Blitter (STRBLT) Engines
This multitexture support provides a superset of the “legacy” one-texture (pre-DirectX 6) texture blend
modes and a large subset of the operations defined in DirectX 6 and the OpenGL ARB multitexture
extensions.
The Multitexture Compositing Unit is capable of combining the interpolated vertex diffuse color, a
constant color value, and up to two texels per pixel in a fully-programmable fashion. Up to three
operations (combinations) can be performed in a pipelined organization, with intermediate storage to
support complex equations, e.g., of the form “A*B + C*D” required for light maps and specular gloss
maps. Separate operations can be performed on color (RGB) and alpha components.
The GMCH contains BLT and STRBLT functionality, a hardware cursor, and an extensive set of 2D
registers and instructions.
GMCH VGA Registers and Enhancements
The 2D registers are a combination of registers defined by IBM* when the Video Graphics Array (VGA)
was first introduced, and others that Intel has added to support graphics modes that have color depths,
resolutions, and hardware acceleration features that go beyond the original VGA standard. The internal
graphics device of the GMCH improves upon VGA by providing additional features that are used
through numerous additional registers.
The GMCH also supports an optional display cache. As an improvement on the VGA standard display
cache port-hole, the GMCH also maps the entire display cache into part of a single contiguous memory
space at a programmable location, providing what is called “linear” access to the display cache. The size
of this memory can be up to 4 MB, and the base address is set via PCI configuration registers.
Alternatively, these buffers may be implemented in system memory (via D.V.M.), thus alleviating the
need for the display cache.
The GMCH ‘s 64-bit BLT engine provides hardware acceleration for many common Windows*
operations. The following are two primary BLT functions: Fixed Blitter (BLT) and Stretch Blitter
(STRBLT). The term BLT refers to a block transfer of pixel data between memory locations. The word
“fixed” is used to differentiate from the Stretch BLT engine. The BLT engine can be used for the
following:
The internal graphics device of the GMCH has instructions to invoke BLT and STRBLT operations,
permitting software to set up instruction buffers and use batch processing as described in the 3D/2D
Instruction Processing (Pipeline Preprocessor) Section. Note that these instructions replace the need to
do PIO directly to BLT and STRBLT registers; this speeds up the operation.
• Move rectangular blocks of data between memory locations
• Data Alignment
• Perform logical operations
Datasheet
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