NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 51

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.5.3.
Datasheet
R
PCICMD    PCI Command Register (Device 1)
Address Offset:
Default:
Access:
This 16-bit register provides basic control over the GMCH’s ability to respond to PCI cycles. The
PCICMD Register in the GMCH disables the GMCH PCI compliant master accesses to system memory.
15:10
15
Addr/Data
(Not Impl)
Bit
Stepping
9
8
7
6
5
4
3
2
1
0
7
Reserved.
Fast Back-to-Back (FB2B)    RO. (Not Implemented). Hardwired to 0.
SERR# Enable (SERRE)     RO. (Not Implemented). Hardwired to 0.
Address/Data Stepping    RO. (Not Implemented). Hardwired to 0.
Parity Error Enable (PERRE)    RO. (Not Implemented). Hardwired to 0.
Video Palette Snooping (VPS)    RO. This bit is hardwired to 0 to disable snooping.
Memory Write and Invalidate Enable (MWIE)    RO. Hardwired to 0. The internal graphics device of
the GMCH does not support memory write and invalidate commands.
Special Cycle Enable (SCE)    RO. This bit is hardwired to 0. The internal graphics device of the
GMCH ignores Special cycles.
Bus Master Enable (BME)    RO. Hardwired to 1 to enable the internal graphics device of the GMCH
to function as a PCI compliant master.
Memory Access Enable (MAE)    R/W. This bit controls the internal graphics device of the GMCH’s
response to memory space accesses.
0 = Disable (default).
1 = Enable.
I/O Access Enable (IOAE)    R/W. This bit controls the internal graphics device of the GMCH’s
response to I/O space accesses.
0 = Disable (default).
1 = Enable.
(Not Impl)
Error En
Parity
6
(Not Impl)
VGA Pal
Sn
5
Reserved (0)
04h−05h
0004h
Read Only, Read/Write
& Inval En
(Not Impl)
Mem WR
4
Descriptions
(Not Impl)
Cycle En
Special
3
Master En
(Enabled)
Bus
2
10
(Not Impl)
Mem Acc
Intel
FB2B
En
9
1
®
82810E (GMCH)
I/O Acc En
(Not Impl)
SERR En
8
0
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